Abstract: A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation.

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline.

Abstract: A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation.

Abstract: A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased.

Abstract: A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.

Abstract: Disclosed is a EEPROM flash memory array utilizing single transistor cells to provide read/write nonvolatile storage. The array includes a plurality of sectors, each oriented along the word line direction, and the sectors may include one or more word lines. An erase select transistor is provided for each sector and each word line includes a pass gate transistor which assists in both the programming and the erase operations.

Abstract: A five volt only E.sup.2 PROM cell including metal bit read and bit ground column lines and polysilicon word select and program row lines. An interconnected word select and stacked gate transistor serially connect the bit read and bit ground lines. The cell also includes a tunneling structure, disposed below the program row line, for charging or uncharging a floating polysilicon gate in the stacked gate transistor. The bit ground line is disconnected from ground during the charging and uncharging operations.

Abstract: A nonvolatile dynamic RAM capable of operating in a dynamic RAM mode and a second, nonvolatile mode, is disclosed. The nonvolatile dynamic RAM has a memory cell having a transfer transistor for coupling a storage capacitor having a floating gate to a bit line. The memory cell holds information by the storage of charge in the storage capacitor and also holds information by the storage of charge in the floating gate. This data can be stored and retrieved in a volatile mode and in a nonvolatile mode. The nonvolatile dynamic RAM has a plurality of these memory cells connected to a bit line which, in turn, is connected to a sense amplifier for determining the presence or absence of storage charges in the storage capacitor of a selected memory cell in the first mode, and for determining the presence or absence of storage charges in the floating gate of the selected memory cell in the second mode.