Abstract: In one example embodiment, an alarm unit for monitoring or detecting presence of an analyte on an analyte sensor comprises a square plastic casing protecting the alarm electronics portion and including a signal processing means, a clip attachment means configured to be separated and attached from the casing and used to attach the unit to clothing. The clip attachment has enough clearance to be used with thick articles of clothing including diapers and has a set of teeth frictionally held against a rubber strip portion located on the casing back so as to also enable secure attachment to very thin articles of clothing. The alarm unit may further comprise a three-way switch located externally for easy alarm chime and alarm volume selection.

Abstract: In one example embodiment, an alarm unit for monitoring or detecting presence of an analyte on an analyte sensor comprises a square plastic casing protecting the alarm electronics portion and including a signal processing means, a clip attachment means configured to be separated and attached from the casing and used to attach the unit to clothing. The clip attachment has enough clearance to be used with thick articles of clothing including diapers and has a set of teeth frictionally held against a rubber strip portion located on the casing back so as to also enable secure attachment to very thin articles of clothing. The alarm unit may further comprise a three-way switch located externally for easy alarm chime and alarm volume selection.

Abstract: An electrolyte sensor that uses conductive elastomer electrodes. Examples of the intended analytes for sensor use include those found in urine, saliva, blood, feces and spinal fluid, although other analytes exist for electrolyte detection. Conductive elastomer trace electrodes are separated by a gap or channel which can be bridged by an electrolyte and thereby complete an electrical circuit to an alarm or other circuitry. Gap or channel distances vary the level of electrical resistance associated with detecting certain analytes.

Abstract: A PLL circuit (401), including a VCO (420) having a trimming port (418) and a tuning port (416), a PLL controller (404), a variable voltage source (408), a voltage measuring circuit (426) and a multiplexer (412, 414, 428), performs automatic trimming of the VCO (420). The PLL circuit (401) accomplishes this by initiating a trimming mode that controls the multiplexer so that it couples the output of the PLL controller (404) to the trimming port (418), and the output of the variable voltage source (408) to the tuning port (416), thereby to phase lock the VCO (420) to the reference frequency signal (421). The PLL circuit (401) then measures, by way of the voltage measuring circuit (426), a voltage at the trimming port (418), switches the PLL circuit (401) to an operational mode, and then adjusts the variable voltage source (408) to be substantially equal to the voltage measured.

Abstract: A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. The fractional divider includes means for compensating the spurs when the fractional numerator N=0. The synthesizer includes means for selecting a reference divisor R such that a non zero value of fractional numerator is produced and such that the generated spurs fall below the side band noise limits of the synthesizer's voltage controlled oscillator.

Abstract: A BIMOS logic gate (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (36) and provides an ECL level output signal (34). A bipolar transistor (20) is biased by a complementary ECL level input signal 32'. The other portion of the differential circuit includes a bipolar transistor (30) that is biased by an ECL level input signal 32. The emitter coupled transistors 20 and 30, receiving complementary ECL level inputs, along with the MOS transistor 36, receiving MOS level inputs, combine to provide logic functions with ECL level outputs 34 and 34'.

Abstract: A frequency synthesizer (10) for providing a modulated output signal (fo) includes a reference frequency signal (fr) and a voltage controlled oscillator (14). For dividing the frequency of the output signal from the voltage controlled oscillator (14) by a divisor, a programmable divider (16) is coupled to the output of the voltage controlled oscillator (14). To produce a phase-locked loop in which the frequency of the output signal from the voltage controlled oscillator (14) is equal to the frequency of the reference frequency (fr) signal multiplied by the divisor, a phase detector (12 ) having a first input coupled to the reference frequency signal (fr), a second input coupled to the output of the programmable divider (16), and an output coupled to the input of the voltage controlled oscillator (14) is also provided. A first integrator (24) for integrating a modulating signal provides an integrated signal and a first control signal.

Abstract: A BIMOS lever convertor (10) comprises a differential circuit having a common biasing network (14). A MOS transistor (16) in one portion of the differential circuit receives a MOS level input signal (32) and provides an ECL level output signal (34). The other portion of the differential circuit includes a bipolar transistor (18) that is biased by the MOS transistor (16). The bipolar transistor (18) operates to provide a complementary ECL level output signal (34') so as to provide a single ended MOS to differential ECL interface suitable for integration in an I.C.

Abstract: A method of programming a ROM for a multiple conversion frequency synthesizer provides a mechanism for avoiding receiver self-quieting. The method includes the steps of searching for frequencies which cause potential receiver self-quieting responses and selecting a second local oscillator frequency suitable for avoiding receiver self-quieting. A single bit of a ROM is used to represent possible second local oscillator frequencies synthesized by the frequency synthesizer which provide either high-side or low-side injection to the second mixer. Finally, the method includes the step of encoding the single second local oscillator frequency determining bit of the ROM appropriately for selecting the local oscillator frequency which avoids receiver self-quieting.

Abstract: A low-voltage, complementary symmetry amplifier arrangement is disclosed which functions effectively on supply voltages down to one volt DC. The amplifier is especially suited for audio processing applications in hand-held personal electronics apparatus, such as pocket radio receivers. The circuit configuration is easily implemented in integrated circuit form and operates efficiently on class B operation with its attendant advantages. The amplifier arrangement is characterized by the use of current sources in the collector and emitter circuits of a differential amplifier and thereby employs current ratios instead of the more conventional voltage levels to selectively control the conduction of associated output devices.