Abstract: This invention is multiply-accumulate circuit supporting a load of the accumulator. During multiply-accumulate operation a partial product generator forms partial produces from the product inputs. An adder tree sums the partial product and the accumulator value. The sum is stored back in the accumulator overwriting the prior value. During load operation an input gate forces one of the product inputs to all 0's. Thus the partial product generator generates partial products corresponding to a zero product. The adder tree adds this zero product to the external load value. The sum, which corresponds to the external load value is stored back in the accumulator overwriting the prior value. A multiplexer at the side input of the adder tree selects the accumulator value for normal operation or the external load value for load operation.

Abstract: This invention is a FFT butterfly circuit. This circuit includes four temporary data registers connected to three memories. The three memories include read/write X and Y memories and a read only twiddle coefficient memory. A multiplier-accumulator forms a product and accumulates the product with one of two accumulator registers. A register file with plural registers is loaded from one of the accumulator registers or the fourth temporary data register. An adder/subtracter forms a selected one of a sum of registers or a difference of registers. A write buffer with two buffers temporarily stores data from the adder/subtracter before storage in the first or second memory. The X and Y memories must be read/write but the twiddle memory may be read only.

Abstract: This invention is a FFT butterfly circuit. This circuit includes four temporary data registers connected to three memories. The three memories include read/write X and Y memories and a read only twiddle coefficient memory. A multiplier-accumulator forms a product and accumulates the product with one of two accumulator registers. A register file with plural registers is loaded from one of the accumulator registers or the fourth temporary data register. An adder/subtracter forms a selected one of a sum of registers or a difference of registers. A write buffer with two buffers temporarily stores data from the adder/subtracter before storage in the first or second memory. The X and Y memories must be read/write but the twiddle memory may be read only.

Abstract: This invention is multiply-accumulate circuit supporting a load of the accumulator. During multiply-accumulate operation a partial product generator forms partial produces from the product inputs. An adder tree sums the partial product and the accumulator value. The sum is stored back in the accumulator overwriting the prior value. During load operation an input gate forces one of the product inputs to all 0's. Thus the partial product generator generates partial products corresponding to a zero product. The adder tree adds this zero product to the external load value. The sum, which corresponds to the external load value is stored back in the accumulator overwriting the prior value. A multiplexer at the side input of the adder tree selects the accumulator value for normal operation or the external load value for load operation.

Abstract: An audio processor is disclosed and includes a sample rate converter and a digital phase-locked-loop module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of filters.

Abstract: An audio processor is disclosed and includes a sample rate converter and a digital phase-locked-loop module in communication with the sample rate converter. The sample rate converter includes a plurality of digital filters, and the digital phase locked loop module includes a phase accumulator having an initialization value determined based at least partially on a filter sequence address associated with the plurality of filters.

Abstract: A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.

Abstract: A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.

Abstract: A method and apparatus for sample rate conversion in an analog to digital converter. Such a method and apparatus include processing that begins by receiving an input digital stream at a first clock rate from an oversampling quantizer (e.g., a sigma delta modulator). The processing continues by integrating the input digital stream over multiple clock cycles at the first clock rate to produce an integrated digital signal. The processing continues by determining when an interpolated digital value of the integrated digital signal is to be passed to a differentiation stage based on a difference between a sample rate conversion value and a reference value. The processing continues by, when the difference is within a targeted range (e.g.

Abstract: A method and apparatus for converting sample rates of digital signals includes processing that begins by receiving an input data stream at a first sample rate. The processing continues by retrieving predetermined integrated samples at the first sampling rate, where the predetermined integrated samples are derived based on a ratio between the first sampling rate and a second sampling rate. The processing then continues by adjusting the retrieved predetermined integrated samples based on data values of the input data stream to produce adjusted integrated samples. The processing continues by differentiating the adjusted integrated samples to produce an output data stream at an output sample rate, wherein the second sample rate is a multiple of the output sample rate.

Abstract: The non-overlap clock circuit of this invention is responsive to a variable input signal for producing a first and second output signal that vary respectively with phases opposite to and the same as the input signal. The circuit comprises a NOR-gate with its first input connected to the variable signal input and its second input to the second signal output of the circuit. The output of the NOR-gate is the first signal output of the circuit. The circuit includes a first means such as an enhancement type FET having a gate and a main current path. The gate is supplied with a first output signal of the circuit and the main current path is connected between ground and the second signal output of the circuit. A second means such as a depletion type FET is also employed with its main current path connected between the variable signal input and the second signal output of the circuit. The second signal output of the circuit is thus driven by the variable input signal through the main current path of the second means.