Patents by Inventor Darrell L. Carder
Darrell L. Carder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160169965Abstract: The present disclosure provides system and method embodiments for generation of capture clock signals. A first and second test circuit receive a first test pattern and a functional clock signal. A first test clock control (TCC) circuit of the first test circuit generates a first capture clock signal that comprises a set of functional clock signal pulses generated according to a first clock pattern of the first test pattern. A second TCC circuit of the second test circuit generates a second capture clock signal that comprises the set of functional clock signal pulses generated according to the first clock pattern. The set of functional clock signal pulses of the second capture clock signal are staggered in time from the set of functional clock signal pulses of the first capture clock signal.Type: ApplicationFiled: December 11, 2014Publication date: June 16, 2016Inventors: DARRELL L. CARDER, RAKESH BAKHSHI, ROBERT N. EHRLICH
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Patent number: 9366724Abstract: The present disclosure provides system and method embodiments for generation of capture clock signals. A first and second test circuit receive a first test pattern and a functional clock signal. A first test clock control (TCC) circuit of the first test circuit generates a first capture clock signal that comprises a set of functional clock signal pulses generated according to a first clock pattern of the first test pattern. A second TCC circuit of the second test circuit generates a second capture clock signal that comprises the set of functional clock signal pulses generated according to the first clock pattern. The set of functional clock signal pulses of the second capture clock signal are staggered in time from the set of functional clock signal pulses of the first capture clock signal.Type: GrantFiled: December 11, 2014Date of Patent: June 14, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Darrell L. Carder, Rakesh Bakhshi, Robert N. Ehrlich
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Patent number: 9069042Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structure.Type: GrantFiled: November 5, 2013Date of Patent: June 30, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Rajesh Raina, Magdy S. Abadir, Darrell L. Carder
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Publication number: 20150128001Abstract: A circuit for efficiently testing digital shadow logic (504, 514) in isolation from an associated non-logic design structure (510) includes a width and delay matched bypass circuit (520) coupled to receive an n-bit input from shadow logic (504) and to generate therefrom an m-bit test output which is selectively connected to replace an m-bit output to the shadow logic (514) from the non-logic design structure (510) in a shadow logic test mode, thereby flexibly emulating the non-logic design structure to allowing separate isolated tests on the shadow logic and on the non-logic design structureType: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Rajesh Raina, Magdy S. Abadir, Darrell L. Carder
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Patent number: 7725788Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.Type: GrantFiled: January 25, 2007Date of Patent: May 25, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Thomas Tkacik, John E. Spittal, Jr., Jonathan Lutz, Lawrence Case, Douglas Hardy, Mark Redman, Gregory Schmidt, Steven Tugenberg, Michael D. Fitzsimmons, Darrell L. Carder
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Patent number: 7346820Abstract: A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.Type: GrantFiled: March 23, 2006Date of Patent: March 18, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Milind P. Padhye, Darrell L. Carder, Bhoodev Kumar, Bart J. Martinec
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Patent number: 7185249Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.Type: GrantFiled: April 30, 2002Date of Patent: February 27, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Thomas Tkacik, John E. Spittal, Jr., Jonathan Lutz, Lawrence Case, Douglas Hardy, Mark Redman, Gregory Schmidt, Steven Tugeberg, Michael D. Fitzsimmons, Darrell L. Carder
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Publication number: 20030204801Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.Type: ApplicationFiled: April 30, 2002Publication date: October 30, 2003Applicant: Motorola, Inc.Inventors: Thomas Tkacik, John E. Spittal, Jonathan Lutz, Lawrence Case, Douglas Hardy, Mark Redman, Gregory Schmidt, Steven Tugeberg, Michael D. Fitzsimmons, Darrell L. Carder