Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

Abstract: A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.

Abstract: A structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.

Abstract: A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.

Abstract: A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.

Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.

Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

Abstract: An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.

Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.

Abstract: A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.

Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.

Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.

Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die by while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.

Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die by while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.