Abstract: A sample-and-hold circuit is provided that includes a plurality of sample-and-hold branches arranged in parallel and each including a buffer and a sample-and-hold block including one or more sample-and-hold cells. The sample-and-hold circuit further includes a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block. The time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period.

Abstract: A pixel circuit wherein a pixel arrangement comprises a pixel comprising a photodetector, an integrator for accumulating a signal from the photodetector, a source following output transistor for amplifying the integrated signal, and a current source for applying a readout current through the output transistor, a voltage regulating circuit comprising an amplifier, a replica transistor dimensioned substantially the same as the output transistor, and a replica current source for providing substantially the readout current through each replica transistor, a gate of the replica transistor is connected with an output node of the amplifier connected with the pixel arrangement, and a source of the replica transistor is connected with a negative input of the amplifier, and with the replica current source, a predefined reference voltage is applicable to a positive input.

Abstract: A sample and hold system, for capturing and reading a sequence of traces of an input signal. The sample and hold system comprising a readout device, a controller, and a sample and hold array of unit cells. The controller is configured for controlling the sample and hold system, such that during an acquisition phase a trace of samples is taken from the input signal in an original sample order and such that the samples are held in the unit cells wherein the samples are assigned to the unit cells in an acquisition order, such that during a consecutive readout phase the samples are read out from the unit cells wherein the order in which the unit cells are read out corresponds with a readout order, and such that the acquisition order and/or the readout order differs from trace to trace.

Abstract: A pixel circuit wherein a pixel arrangement comprises a pixel comprising a photodetector, an integrator for accumulating a signal from the photodetector, a source following output transistor for amplifying the integrated signal, and a current source for applying a readout current through the output transistor, a voltage regulating circuit comprising an amplifier, a replica transistor dimensioned substantially the same as the output transistor, and a replica current source for providing substantially the readout current through each replica transistor, a gate of the replica transistor is connected with an output node of the amplifier connected with the pixel arrangement, and a source of the replica transistor is connected with a negative input of the amplifier, and with the replica current source, a predefined reference voltage is applicable to a positive input.

Abstract: An optical detector for converting an optical signal into an electrical signal comprises a photo sensitive device adapted for receiving the optical signal and converting it into an electrical signal. The optical detector moreover comprises a bias compensation circuit and a control circuit. The control circuit is adapted to control the bias compensation circuit to maintain a bias level across the photo sensitive device above a minimum bias level, and to turn the bias compensation circuit off when a current through the photo sensitive device is so small that the bias level across the photo sensitive device is above the minimum bias level.

Abstract: A sample and hold system, for capturing and reading at least one input signal. The system comprises a readout device, a controller, an array of segments comprising a plurality of unit cells and a dummy unit cell, and segment switches between the segments and the readout device. The controller is adapted for controlling the system such that: during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells; during a readout phase the samples in the unit cells or in the dummy unit cells of a segment are read out by readout device; after opening or closing the segment switches the dummy unit cell, is the first cell which is read out by the readout device.

Abstract: The present invention relates to a sample-and-hold circuit comprising a plurality of sample-and-hold branches arranged in parallel and each comprising a buffer and a sample-and-hold block comprising one or more sample-and-hold cells characterised in that said sample-and-hold circuit further comprises a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block, wherein the time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period.

Abstract: A sample and hold system, for capturing and reading at least one input signal. The system comprises a readout device, a controller, an array of segments comprising a plurality of unit cells and a dummy unit cell, and segment switches between the segments and the readout device. The controller is adapted for controlling the system such that: during an acquisition phase a trace of samples is taken from the input signal and held in the unit cells; during a readout phase the samples in the unit cells or in the dummy unit cells of a segment are read out by readout device; after opening or closing the segment switches the dummy unit cell, is the first cell which is read out by the readout device.

Abstract: A sample and hold system, for capturing and reading a sequence of traces of an input signal. The sample and hold system comprising a readout device, a controller, and a sample and hold array of unit cells. The controller is configured for controlling the sample and hold system, such that during an acquisition phase a trace of samples is taken from the input signal in an original sample order and such that the samples are held in the unit cells wherein the samples are assigned to the unit cells in an acquisition order, such that during a consecutive readout phase the samples are read out from the unit cells wherein the order in which the unit cells are read out corresponds with a readout order, and such that the acquisition order and/or the readout order differs from trace to trace.

Abstract: A phase-locked loop circuit includes one loop for regulating phase of a VCO with respect to a reference source. In another loop, VCO frequency is compared to frequency of a crystal oscilator. Digital counters divide the frequency of the crystal oscillator and VCO to a common reference frequency. Once the frequency loop is locked, the counter at the output of the crystal oscillator is bypassed. The counter is bypassed by a flip-flop circuit clocked by the crystal oscillator and receiving a scaled input from the VCO. While the VCO frequency error is in the frequency range of correction capability of the Phase-locked loop, the output of the flip-flop will duplicate the output of the counter. Thus, the counter can be bypassed and shut off.

Abstract: A phase-locked loop circuit includes one loop for regulating phase of a VCO with respect to a reference source. In another loop, VCO frequency is compared to frequency of a crystal oscillator. Digital counters divide the frequency of the crystal oscillator and VCO to a common reference frequency. Once the frequency loop is locked, the counter at the output of the crystal oscillator is bypassed. The counter is bypassed by a flip-flop circuit clocked by the crystal oscillator and receiving a scaled input from the VCO. While the VCO frequency error is in the frequency range of correction capability of the phase-locked loop, the output of the flip-flop will duplicate the output of the counter. Thus, the counter can be bypassed and shut off.

Abstract: A technique controls a charge pump bias circuit in a phase-locked loop (PLL) circuit. The charge pump bias circuit biases a charge pump circuit. A digital phase detector generates direction control signals based on reference and pre-scale count signals from reference and pre-scale counting circuits, respectively. The direction control signals control direction of current pumped by the charge pump circuit. A charge pump enable generator generates an enable signal based on look-ahead reference and pre-scale count signals from the reference and pre-scale counting circuits, respectively. The look-ahead reference and pre-scale count signals are generated before the corresponding reference and pre-scale count signals by a predetermined time interval. The enable signal powers down the charge pump bias circuit after the charge pump circuit pumps the current.