Patents by Inventor Darrell Miles

Darrell Miles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070164426
    Abstract: An apparatus for implementing integrated circuit cooling during testing and image-based analysis thereof includes a lid configured to define a cavity surrounding an integrated circuit die, the die mounted to a module substrate. One or more fluid passages are defined within the lid, wherein the passages facilitate the flow of a cooling liquid through said cavity and over the integrated circuit die, and a transparent window is formed within the lid so as to facilitate viewing of the integrated circuit die.
    Type: Application
    Filed: January 18, 2006
    Publication date: July 19, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patrick McGinnis, Darrell Miles, Richard Oldrey, John Sylvestri, Manuel Villalobos
  • Publication number: 20060097742
    Abstract: An apparatus for facilitating single die backside probing of semiconductor devices includes a chip holder configured for receiving a single integrated circuit die attached thereto, the chip holder maintained in flexible engagement in an X-Y orientation with respect to a lift plate. A lift ring is coupled to the lift plate, the lift ring configured to facilitate adjustment of the lift plate and the chip holder in a Z-direction.
    Type: Application
    Filed: November 10, 2004
    Publication date: May 11, 2006
    Inventors: Patrick McGinnis, Darrell Miles, Richard Oldrey, John Sylvestri, Manuel Villalobos
  • Publication number: 20060030160
    Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
    Type: Application
    Filed: October 3, 2005
    Publication date: February 9, 2006
    Inventors: Terence Kane, Darrell Miles, John Sylvestri, Michael Tenney
  • Publication number: 20050148157
    Abstract: A method and system for backside unlayering a semiconductor device to expose FEOL semiconductor features of the device for subsequent electrical and/or physical probing. A window is formed within a backside substrate layer of the semiconductor. A collimated ion plasma is generated and directed so as to contact the semiconductor only within the backside window via an opening in a focusing shield. This focused collimated ion plasma contacts the semiconductor, only within the window, while the semiconductor is simultaneously being rotated and tilted by a temperature controlled stage, for uniform removal of semiconductor layering such that the semiconductor features, in a location on the semiconductor corresponding to the backside window, are exposed. Backside unlayering of the invention may be enhanced by CAIBE processing.
    Type: Application
    Filed: January 6, 2004
    Publication date: July 7, 2005
    Inventors: Terence Kane, Darrell Miles, John Sylyestri, Michael Tenney
  • Publication number: 20050073333
    Abstract: A method for implementing backside probing of a semiconductor device includes isolating an identified defect area on a backside of the semiconductor device, and milling the identified defect area to an initial depth. Edges of the identified defect area are masked, wherein unmasked semiconductor material, beginning at the initial depth, is etched for a plurality of timed intervals until one or more active devices are reached. The one or more active devices are electrically probed.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 7, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Barbara Averill, Terence Kane, Darrell Miles, Richard Oldrey, John Sylvestri
  • Patent number: 6718537
    Abstract: A method of executing test cases with a parallel test segment of a test sequence, is disclosed. Initially, a test sequence is defined that includes a parallel test segment including at least a first test case and a second test case. A cycle time of the parallel test segment is determined where the determined cycle time is greater than the execution time of either the first or second test cases. The test sequence is then executed repeatedly. During each execution of the test sequence, the start point of the first and second test cases within the parallel test segment are varied with respect to one another preferably in a random fashion.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventor: James Darrell Miles
  • Patent number: 6654911
    Abstract: A method, system, and computer program product for generating test sequences are disclosed. Initially, a graphical user interface is invoked to display a list of preexisting test cases. A first test case is selected from the list of test cases and to create a first instance of the first test case, which is added to the test sequence. The test sequence is displayed in a test sequence portion of the graphical user interface. A subsequent test case is then selected from the list of test cases to create an instance of the subsequent test case, which is also added to the test sequence. The GUI may permit the modification of a parameter of the first test case by invoking a test case editor from the GUI. In one embodiment, the subsequent test case and the first case are the same such that first and second instances of the first test cases are included in the test sequence.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: November 25, 2003
    Assignee: International Business Machines Corporation
    Inventor: James Darrell Miles