Patents by Inventor Darrell R. Kay

Darrell R. Kay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 3975624
    Abstract: A two's complement subtractor using a one bit full adder for the most significant bit. A series of arithmetic logic units are fed by the respective binary bits to be subtracted with the logic units effecting internal two's complementing of the subtrahend thereby permitting adding to the minuend. The most significant input bits are in addition fed to a one bit full adder together with the carry in bit from the last arithmetic logic unit of the series. The one bit full adder outputs the most significant bit or the sign resulting from the subtraction and this adder can have either internal inversion of the subtrahend or an inverter can precede the subtrahend input.
    Type: Grant
    Filed: May 19, 1975
    Date of Patent: August 17, 1976
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: Darrell R. Kay