Abstract: The present invention teaches a variety of methods, data structures and apparatus for use in representing and traversing hierarchical netlists. According to a first embodiment of the present invention, a hierarchical netlist which represents an electronic device is stored in a computer readable medium and includes a module data structure and a hierarchical data structure. The module data structure includes a first module and a list identifying each instance of the first module present in the hierarchical netlist. The hierarchical point data structure represents a first hierarchical element in the hierarchical netlist and is arranged to identify a selected device element represented in the first module. Additionally, the hierarchical point data structure is capable of identifying a plurality of unique occurrences of separate but identical device elements that are represented by the first hierarchical element.

Abstract: A method and apparatus for simulation of a hardware design using a cycle-based event-driven simulation. The present invention also provides for a measuring technique for estimating the potential performance gain obtained by using traditional simulation techniques as opposed to the cycle-based event-driven simulation technique of the present invention. The result of the measuring technique is provided for a user as a tool in determining which technique they would like to use for the simulation of their hardware design.

Abstract: The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.