Abstract: Hybrid memory architecture technologies are described. In accordance with embodiments disclosed herein, there is provided a processing device having a core and a memory controller communicably coupled to the core to receive a request to fetch data. The memory controller is communicably coupled to a hybrid memory architecture including a near memory, wherein the near memory is divided into a flat memory region and a cache memory region.

Abstract: A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.

Abstract: A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.

Abstract: In some embodiments, a system and method for making a scalable clock gearing mechanism may allow multiple devices operating on different clock speeds to communicate. In an embodiment, a mechanism may be used to input data clocked on a first clock frequency and output the data on a second clock frequency. The mechanism may temporarily store the data until the next clock cycle of the second clock. Further, the mechanism may make use of multiple inputs or outputs to input or output multiple data units during a single clock cycle to keep the delay between the arrival and departure of the data small.

Abstract: An apparatus (11) causes invalid data to be read again from a memory device (12, 13) before being read by a device (10). A transaction queue (22) stores pending and dispatched device transactions, the queue includes an input for receiving (21) transactions, an output for dispatching (26) transactions, a pointer for pending transactions, and a pointer for dispatched transactions. A master controller (42) responds to an invalid data signal by preventing the transaction queue from dispatching pending transactions to the memory device, by causing the transaction queue to dispatch again the device read transaction which resulted in the invalid data and, subsequently, by causing the data which was read again from the memory device to be accepted by the destination device, by setting the dispatched transaction pointer to the pending transactions pointer, and by enabling the transaction queue to dispatch pending transactions to the memory device.

Abstract: In some embodiments, a system and method for mapping the logical chip selects to a physical chip select. A chip select remapping unit receives logical chip select associated with a dual in-line memory module. The chip select remapping unit converts the logical chip select vector through a redirection table that maps the logical memory ranks to available physical memory ranks.

Abstract: In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required ¼ clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.

Abstract: Write pointer error recovery systems and methods are provided. A write pointer from a write pointer circuit may cause a demultiplexer circuit to direct data from a memory cell to a desired bit location in a register. A read pointer may cause a multiplexer circuit to select data from a desired bit location in the register to provide as output data or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal. The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line. Other embodiments are also claimed and described.

Abstract: A write pointer (21) from a write pointer circuit (13) may cause a demultiplexer circuit (12) to direct data from a memory cell (11A–11N) to a desired bit location (0–4) in a register 14. A read pointer (20) may cause a multiplexer circuit (15) to select data from a desired bit location in the register to provide as output data (19) or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal (17). The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line (18).