Patents by Inventor Darrell Truhitte
Darrell Truhitte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049843Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.Type: GrantFiled: April 18, 2019Date of Patent: June 29, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Phillip Celaya, James P. Letterman, Jr., Robert L. Marquis, Darrell Truhitte
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Patent number: 11037903Abstract: A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.Type: GrantFiled: December 30, 2016Date of Patent: June 15, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell Truhitte
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Publication number: 20190244928Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.Type: ApplicationFiled: April 18, 2019Publication date: August 8, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Phillip CELAYA, James P. LETTERMAN, JR., Robert L. MARQUIS, Darrell TRUHITTE
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Patent number: 10304798Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.Type: GrantFiled: January 12, 2018Date of Patent: May 28, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Phillip Celaya, James P. Letterman, Jr., Robert L. Marquis, Darrell Truhitte
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Publication number: 20180138144Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.Type: ApplicationFiled: January 12, 2018Publication date: May 17, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Phillip CELAYA, James P. LETTERMAN, JR., Robert L. MARQUIS, Darrell TRUHITTE
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Patent number: 9899349Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.Type: GrantFiled: March 7, 2016Date of Patent: February 20, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Phillip Celaya, James P Letterman, Jr., Robert L. Marquis, Darrell Truhitte
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Patent number: 9892952Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: July 25, 2014Date of Patent: February 13, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell Truhitte, James P. Letterman, Jr.
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Publication number: 20170110436Abstract: A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.Type: ApplicationFiled: December 30, 2016Publication date: April 20, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell TRUHITTE
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Patent number: 9559007Abstract: A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages.Type: GrantFiled: September 30, 2015Date of Patent: January 31, 2017Assignee: SEMICONDUDTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell Truhitte
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Publication number: 20160190095Abstract: Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Phillip CELAYA, James P. LETTERMAN, JR., Robert L. MARGUIS, Darrell TRUHITTE
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Patent number: 8987054Abstract: In one embodiment, methods for making semiconductor devices are disclosed.Type: GrantFiled: March 15, 2013Date of Patent: March 24, 2015Assignee: Semiconductor Components Industries, L.L.C.Inventor: Darrell Truhitte
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Publication number: 20140273356Abstract: In one embodiment, methods for making semiconductor devices are disclosed.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventor: Darrell Truhitte
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Publication number: 20050037544Abstract: A method of forming a leadframe (10) provides blocking fulcrums (21,23) adjacent to the leads (12,13,14, and 15). During the process of encapsulating the leadframe (10), the blocking fulcrums (21,23) restrict encapsulating material from exiting the mold cavity and from attaching to the leads (12,13,14, and 15).Type: ApplicationFiled: August 11, 2003Publication date: February 17, 2005Inventors: Guan Quah, Darrell Truhitte
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Patent number: 5585281Abstract: A method of forming leads and providing a final test of a semiconductor package including an electronic circuit therein, the package having unformed leads. A forming and testing station is provided including a support for receiving the package, and dies movably positioned adjacent the support for contacting and forming the leads with test equipment connected to the dies. The semiconductor package is positioned on the support, and the leads of the package are contacted with the dies to connect the test equipment to the leads for testing the electronic circuitry in the package and to form the leads with this contacting step as the final manufacturing step.Type: GrantFiled: February 3, 1995Date of Patent: December 17, 1996Assignee: Motorola, Inc.Inventors: Darrell Truhitte, Theodore R. Golubic, Maureen Sugai