Patents by Inventor Darren Miller Jones

Darren Miller Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configurable co-processor interface
    Patent number: 7886129
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: February 8, 2011
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue
  • Configurable co-processor interface
    Patent number: 7698533
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: April 13, 2010
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue
  • Configurable co-processor interface
    Patent number: 7287147
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order).
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: October 23, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue
  • Configurable out-of-order data transfer in a coprocessor interface
    Patent number: 7237090
    Abstract: An interface for transferring data between a central processing unit (CPU) and a plurality of coprocessors is provided. The interface includes an instruction bus and a data bus. The instruction bus is configured to transfer instructions to the plurality of coprocessors in an instruction transfer order, where particular instructions designate and direct one of the plurality of coprocessors to transfer the data to/from the CPU. The data bus is configured to subsequently transfer the data. Data order signals within the data bus prescribe a data transfer order that differs from the instruction transfer order by prescribing a transfer corresponding to a specific outstanding particular instruction, where the data transfer order is relative to outstanding instructions. The outstanding instructions are those of the particular instructions transferred to the one of the plurality of coprocessors that have not completed a data transfer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: June 26, 2007
    Assignee: Mips Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue
  • Tracing out-of order load data
    Patent number: 7168066
    Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 23, 2007
    Assignee: MIPS Technologies, Inc.
    Inventors: Radhika Thekkath, George Michael Uhler, Franz Treue, Lawrence Henry Hudepohl, Darren Miller Jones
  • Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions
    Patent number: 6754804
    Abstract: A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group supports different types of instructions, such as arithmetic instructions, or data transfer instructions. The coprocessor interface has an instruction transfer signal group for transferring different instructions from the CPU to the multi-issue coprocessor, sequentially or in parallel, an issue group designator for specifying an issue path within the multi-issue coprocessor for execution of the instructions, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instructions, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: June 22, 2004
    Assignee: MIPS Technologies, Inc.
    Inventors: Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue