Abstract: An electronic distance recorder configured to be coupled to a wheel hub of a vehicle, the electronic distance recorder comprising: means for determining distance travelled by the vehicle; means for storing a current vehicle odometer value; means for accruing the current vehicle odometer value based on the distance travelled by the vehicle; a receiver for receiving license data representative of a vehicle license issued for the vehicle; and an electronic display configured to display an indication of the validity of the vehicle license. Vehicle information recorders, communication devices and power generators are also disclosed.

Abstract: An electronic distance recorder configured to be coupled to a wheel hub of a vehicle, the electronic distance recorder comprising: means for determining distance travelled by the vehicle; means for storing a current vehicle odometer value; means for accruing the current vehicle odometer value based on the distance travelled by the vehicle; a receiver for receiving license data representative of a vehicle license issued for the vehicle; and an electronic display configured to display an indication of the validity of the vehicle license. Vehicle information recorders, communication devices and power generators are also disclosed.

Abstract: A thermoelectric deicer sheet comprising a flexible sheet fabricated of static cling vinyl embedded with heater elements with a cord extending therefrom with a 12 volt adapter to plug into a vehicle's cigarette lighter and a user control unit having a means to set the temperature, time of initiation and duration of activity thereof. The sheet is applied to the interior surface of the windshield by applying pressure thereagainst to form a static bond therebetween and is peeled off when operation is complete.

Abstract: A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components.

Abstract: A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: A cryptographic processing system includes a cipher circuit and hash circuit. An input control unit and output control unit work together to process data packets in a pipelined manner wherein the data packets move through the processing system in a single-pass. The input control unit manages data received from a read interface and the initiation of cipher processing of the data in the cipher circuit. The output control unit manages data output to a write interface and the hash processing of the data in the hash circuit. Data moves through the cipher circuit in clear data and cipher data form so that the output control unit may selectively send clear data and/or cipher data to the hash circuit and to an output FIFO memory buffer, which handles final processing under the control of the output control unit prior to sending fully processed data to the write interface.

Abstract: An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.