Abstract: An electronic system such as a processor or computer system includes circuitry that supports a plurality of clock modes. The clock modes may be used for, for example, testing for critical paths. The clock modes include a variety of clock signal variations that may be utilized such as cycle stretch clock mode, pulse or delay fault mode, and stop mode which provide substantial flexibility in support of a multitude of tests. In one embodiment, a processor of an electronic system includes test clock mode circuitry to support and utilize test clock modes without dependence on an external bypass clock signal operating at processor operational frequencies. Furthermore, the processor implements the test clock modes at full processor operational frequencies. Additionally, a phase-locked loop is utilized to synchronize test mode clock signals with a reference clock signal to, for example, facilitate realistic operational conditions and acquisition of accurate test results.

Abstract: A clock generating circuit includes a clock generator and a cycle controller. The clock generator is coupled to receive a reference oscillating signal. The clock generator provides a clock signal responsive to the reference oscillating signal. The cycle controller is coupled to provide a cycle control signal to the clock generator. The clock generator stretches a cycle of the clock signal responsive to a first value of the cycle control signal.