Patents by Inventor Darren S. Jue

Darren S. Jue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180203811
    Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on cach of the lanes.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
  • Publication number: 20180189201
    Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
    Type: Application
    Filed: December 21, 2017
    Publication date: July 5, 2018
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • Patent number: 10002095
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: March 28, 2015
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman V. Iyer
  • Publication number: 20180095927
    Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Rahul C. Shah, Arvind A. Kumar
  • Patent number: 9916266
    Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: March 13, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
  • Patent number: 9892086
    Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Rahul Shah, Arvind Kumar
  • Patent number: 9697158
    Abstract: A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • Publication number: 20170116148
    Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 27, 2017
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman V. Iyer
  • Publication number: 20170109315
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20170109296
    Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Applicant: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • Patent number: 9626321
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • Publication number: 20170097907
    Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.
    Type: Application
    Filed: August 15, 2016
    Publication date: April 6, 2017
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
  • Patent number: 9612986
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman Iyer
  • Publication number: 20170083476
    Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
    Type: Application
    Filed: June 27, 2016
    Publication date: March 23, 2017
    Inventors: Venkatraman Iyer, Darren S. Jue, Rahul Shah, Arvind Kumar
  • Patent number: 9600431
    Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Sitaraman V. Iyer
  • Publication number: 20160378711
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Application
    Filed: May 27, 2016
    Publication date: December 29, 2016
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • Patent number: 9418035
    Abstract: Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a predefined sequence on each of the lanes.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Ashish Gupta
  • Patent number: 9378171
    Abstract: A serial data link is to be adapted during initialization of the link. Adaptation of the link is to include receiving a pseudorandom binary sequence (PRBS) from a remote agent, analyzing the PRBS to identify characteristics of the data link, and generating metric data describing the characteristics.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 28, 2016
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Rahul Shah, Arvind Kumar
  • Patent number: 9355058
    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Debendra Das Sharma, Jeffrey C. Swanson
  • Patent number: 9280507
    Abstract: A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: March 8, 2016
    Assignee: INTEL CORPORATION
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship