Abstract: A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The disconnected elements can be connected to the plurality of interconnected elements after the clock distribution path is tested in connection with the circuit. In one embodiment, the disconnected elements include a capacitor, an interconnect, and a buffer. In an alternative embodiment, the plurality of interconnected elements include a buffer, an interconnect and a capacitor.

Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in regions the semiconductor substrate.

Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in region the semiconductor substrate.

Abstract: A delay circuit. The delay circuit includes a first circuit, a falling edge delay circuit and a rising edge delay circuit. The first circuit includes a circuit input for receiving a reference signal and a circuit output for outputting a delayed signal. The falling edge delay circuit is coupled to the first circuit to control delay of a falling edge of the reference signal. The rising edge delay circuit is coupled to the first circuit to control delay of a rising edge of the reference signal.

Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in regions the semiconductor substrate.

Abstract: A modifiable circuit structure and its method of formation are disclosed. The modifiable circuit structure electrically couples one portion of an interconnect with another portion of the interconnect through vias disposed in a dielectric layer. The combination of the modifiable circuit structure, the interconnect portions, and the vias provide a signal path between transistors in an integrated circuit. In one embodiment the modifiable circuit structure is a polysilicon feature formed over regions of a semiconductor substrate. In an alternative embodiment, the modifiable circuit structure is a diffusion region formed in region the semiconductor substrate.

Abstract: A clock shrink circuit has an inverting first matching stage which is responsive to an input clock signal to generate a first inverted signal having a first matching delay. The first matching delay is a difference between a first rise and a first fall propagation time of the first matching stage. An inverting first pull-up stage is coupled to the first matching stage and is responsive to the first inverted signal to generate a second inverted signal having a first pull-up delay which is substantially reduced by the first matching delay. The first pull-up delay is a difference between a second rise and a second fall propagation time of the first pull-up stage.

Abstract: A delay circuit. The delay circuit includes a first circuit, a falling edge delay circuit and a rising edge delay circuit. The first circuit includes a circuit input for receiving a reference signal and a circuit output for outputting a delayed signal. The falling edge delay circuit is coupled to the first circuit to control delay of a falling edge of the reference signal. The rising edge delay circuit is coupled to the first circuit to control delay of a rising edge of the reference signal.

Abstract: A circuit and method to automatically identify and manipulate a pulse in each of a sequence of clocking signals for an integrated circuit includes a clock manipulation circuit to manipulation the identified pulse including to shrink or otherwise alter the identified pulse; and a pulse identification circuit to automatically and algorithmically identify each pulse to be shrunk.

Abstract: The present invention is related to method and apparatus for clock shrinking that includes a detector, a controller, a switching device, and a buffer. The detector includes one or more counters and detects activation of a trigger. The trigger starts and stops the counters. The controller generates select signals based on output from the counters. The switching device receives vectors and receives the select signals from the controller and outputs the vectors in a sequence based on the select signals. The buffer receives a clock signal and the sequence of vectors and outputs one or more shrunk clock pulses in the clock signal based on the received vectors continuously while the trigger is active. A mode selects the desired shrinking pattern for the clock pulses. The shrinking delays in time or advances in time the rising edge and/or the falling edge of the clock pulses.

Abstract: An apparatus and a method are disclosed to save on the integrated circuit die(s) the state of the scan latches coupled to an integrated circuit in a memory unit during an exercise of the integrated circuit by a coupled tester, to compare on the die the saved states to the state of the scan latches in a subsequent exercise of the integrated circuit, and to transmit the result of the comparison to the tester, rather to have to transmit to the tester the scan latch states for a comparison analysis after each exercise of the integrated circuit. The apparatus and method include deriving on the die a signature of the saved scan latch states, and comparing on the die the signature of an exercise of the integrated circuit and subsequently exercise of the integrated circuit. The invention also includes generating on the die a scan latch latching clock for consecutively exercising the integrated circuit without determining off the die, and sending to the die, for each iteration, the latching clock.

Abstract: A clock shrink circuit has an inverting first matching stage which is responsive to an input clock signal to generate a first inverted signal having a first matching delay. The first matching delay is a difference between a first rise and a first fall propagation time of the first matching stage. An inverting first pull-up stage is coupled to the first matching stage and is responsive to the first inverted signal to generate a second inverted signal having a first pull-up delay which is substantially reduced by the first matching delay. The first pull-up delay is a difference between a second rise and a second fall propagation time of the first pull-up stage.

Abstract: The present invention is related to method and apparatus for clock shrinking that includes a detector, a controller, a switching device, and a buffer. The detector includes one or more counters and detects activation of a trigger. The trigger starts and stops the counters. The controller generates select signals based on output from the counters. The switching device receives vectors and receives the select signals from the controller and outputs the vectors in a sequence based on the select signals. The buffer receives a clock signal and the sequence of vectors and outputs one or more shrunk clock pulses in the clock signal based on the received vectors continuously while the trigger is active. A mode selects the desired shrinking pattern for the clock pulses. The shrinking delays in time or advances in time the rising edge and/or the falling edge of the clock pulses.

Abstract: A circuit and method to automatically identify and manipulate a pulse in each of a sequence of clocking signals for an integrated circuit includes a clock manipulation circuit to manipulation the identified pulse including to shrink or otherwise alter the identified pulse; and a pulse identification circuit to automatically and algorithmically identify each pulse to be shrunk.

Abstract: An apparatus and a method are disclosed to save on the integrated circuit die(s) the state of the scan latches coupled to an integrated circuit in a memory unit during an exercise of the integrated circuit by a coupled tester, to compare on the die the saved states to the state of the scan latches in a subsequent exercise of the integrated circuit, and to transmit the result of the comparison to the tester, rather to have to transmit to the tester the scan latch states for a comparison analysis after each exercise of the integrated circuit. The apparatus and method include deriving on the die a signature of the saved scan latch states, and comparing on the die the signature of an exercise of the integrated circuit and subsequently exercise of the integrated circuit. The invention also includes generating on the die a scan latch latching clock for consecutively exercising the integrated circuit without determining off the die, and sending to the die, for each iteration, the latching clock.

Abstract: A clock network comprises a clock distribution path coupled to a circuit. The clock distribution path and the circuit are formed on a substrate. The clock distribution path comprises a plurality of interconnected elements and one or more disconnected elements. The disconnected elements can be connected to the plurality of interconnected elements after the clock distribution path is tested in connection with the circuit. In one embodiment, the disconnected elements include a capacitor, an interconnect, and a buffer. In an alternative embodiment, the plurality of interconnected elements include a buffer, an interconnect and a capacitor.