Patents by Inventor Darren T. Murley

Darren T. Murley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6566179
    Abstract: A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8″) electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8′). The method comprising the steps of applying a foil (2) comprising a crystallization enhancing material (CEM) and depositing the semiconductor layer (4) over a supporting substrate (1); and heating the semiconductor layer (4) so as to crystallize the semiconductor layer (4) from regions exposed to the CEM of the foil (2). The method may further comprise the step of providing a patterned barrier layer (3) between the foil (2) and the semiconductor layer (4) wherein the semiconductor layer (4) is crystallized from regions exposed through vias in the barrier layer (3) to the CEM of the foil (2).
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: May 20, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Darren T. Murley, Michael J. Trainor
  • Patent number: 6414369
    Abstract: A thin film capacitor is provided with a thin film protection element to protect the capacitor from damage that can result due to the occurrence of an electrostatic discharge event. The thin film capacitor includes two conductive film portions forming capacitor plates and a dielectric film forming the capacitor dielectric. The protection element may take the form of a thin film diode or a series of thin film diodes connected electrically in parallel with the thin film capacitor. The whole device can be fabricated using a stoichiometric silicon nitride layer to produce the capacitor dielectric and a non-stoichiometric silicon rich silicon nitride layer to provide the diode semiconductor material. One diode is formed by one capacitor plate, the semiconductor layer and an upper diode contact.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: July 2, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Stephen J. Battersby, Darren T. Murley, John M. Shannon
  • Publication number: 20010024866
    Abstract: A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8″) electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8′). The method comprising the steps of applying a foil (2) comprising a crystallisation enhancing material (CEM) and depositing the semiconductor layer (4) over a supporting substrate (1); and heating the semiconductor layer (4) so as to crystallise the semiconductor layer (4) from regions exposed to the CEM of the foil (2). The method may further comprise the step of providing a patterned barrier layer (3) between the foil (2) and the semiconductor layer (4) wherein the semiconductor layer (4) is crystallised from regions exposed through vias in the barrier layer (3) to the CEM of the foil (2).
    Type: Application
    Filed: March 21, 2001
    Publication date: September 27, 2001
    Applicant: U.S. Philips Corporation
    Inventors: Darren T. Murley, Michael J. Trainor