Patents by Inventor Darryl Gene Walker

Darryl Gene Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Double gate DRAM memory cell having reduced leakage current
    Patent number: 6661702
    Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel region (324). A top gate (318) is disposed over the channel region (324) and a bottom gate (310) is disposed below the channel region (324). The top gate (318) and bottom gate (310) are commonly driven to provide greater control of the pass transistor (302) operation, including an off state with reduced source-to-drain leakage. The DRAM array (400) includes memory cells (414) having pass transistors (500) with double-gate structures. Memory cells (414) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (600). The DRAM array (400) further includes a strapping area that is void of memory cells.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 9, 2003
    Inventor: Darryl Gene Walker
  • Random access memory cell having double-gate access transistor for reduced leakage current
    Patent number: 6661699
    Abstract: A dynamic random access memory (DRAM) cell and associated array are disclosed. The DRAM cell (300) includes a storage capacitor (304) and a pass transistor (302). The pass transistor (302) includes a source region (322), drain region (320) and channel region (324). A top gate (318) is disposed over the channel region (324) and a bottom gate (310) is disposed below the channel region (324). The top gate (318) and bottom gate (310) are commonly driven to provide greater control of the pass transistor (302) operation, including an off state with reduced source-to-drain leakage. The DRAM array (400) includes memory cells (414) having pass transistors (500) with double-gate structures. Memory cells (414) within the same row are commonly coupled to a top word line and bottom word line. The resistance of the top and bottom word lines is reduced by a word line strap layer (600). The DRAM array (400) further includes a strapping area that is void of memory cells.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: December 9, 2003
    Inventor: Darryl Gene Walker