Abstract: A system for providing a high speed digital communication path between the processor of a host computer and the processors of one or more remote computers. The high speed digital communication path allows a remote computer to efficiently share the resources of the larger host computer such as high speed magnetic disk drives and printers. A host interface located at the host computer is connected to the internal host bus of the host computer. The host interface includes a host port and components which provide for the transfer of data from the host bus to the host port. The data bits presented at the host port are arranged in a parallel format. A communication cable conveys the parallel data bits from the host port to a remote port in a remote interface at a remote computer. The remote interface provides a random access memory and components for transferring data from the remote bus to the random access memory and vice-versa. Data bits presented at the remote port are also conveyed to the random access memory.

Abstract: A system and method for allowing dynamic configuration of the translation entries within a memory management system of a computer. In the disclosed embodiment, portions of a logical address from a CPU are defined as offset, page, volume/page, and volume fields. The offset field is presented unaltered to a main memory to select a specific location within a page of memory. The page field forms a first portion of the address of a selected entry in the translation memory. The volume/page field is combined with the contents of a base register as specified by the contents of a mask register to form the remaining portion of the address of a selected entry in the translation memory. The volume field and volume/page fields are compared to one or more tags stored in the translation memory to determine if a match exists. If a match exists, the frame pointer associated with the matching tag is output to main memory as the physical address of the frame containing the desired page.