Patents by Inventor Darryl Restaino
Darryl Restaino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7691736Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.Type: GrantFiled: February 10, 2006Date of Patent: April 6, 2010Assignee: Infineon Technologies AGInventors: Michael Beck, John A. Fitzsimmons, Karl Hornik, Darryl Restaino
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Publication number: 20070215842Abstract: An aqueous seeding solution of palladium acetate, acetic acid and chloride.Type: ApplicationFiled: May 22, 2007Publication date: September 20, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Darryl Restaino, Donald Canaperi, Judith Rubino, Sean Smith, Richard Henry, James Fluegel, Mahadevaiyer Krishnan
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Publication number: 20070190804Abstract: Embodiments of the invention provide a semiconductor device having dielectric material and its method of manufacture. A method comprises a short (?2 sec) flash activation of an ILD surface followed by flowing a precursor such as silane, DEMS, over the activated ILD surface. The precursor reacts with the activated ILD surface thereby selectively protecting the ILD surface. The protected ILD surface is resistant to plasma processing damage. The protected ILD surface eliminates the requirement of using a hard mask to protect a dielectric from plasma damage.Type: ApplicationFiled: February 10, 2006Publication date: August 16, 2007Inventors: Michael Beck, John Fitzsimmons, Karl Hornik, Darryl Restaino
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Publication number: 20070148958Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: August 4, 2006Publication date: June 28, 2007Inventors: Lawrence Clevenger, Stefanie Chiras, Timothy Dalton, James Demarest, Derren Dunn, Chester Dziobkowski, Philip Flaitz, Michael Lane, James Lloyd, Darryl Restaino, Thomas Shaw, Yun-Yu Wang, Chih-Chao Yang
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Publication number: 20070128882Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.Type: ApplicationFiled: February 5, 2007Publication date: June 7, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Son Nguyen, Sarah Lane, Jia Lee, Kensaku Ida, Darryl Restaino, Takeshi Nogami
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Publication number: 20060202311Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: ApplicationFiled: March 8, 2005Publication date: September 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Son Nguyen, Sarah Lane, Eric Liniger, Kensaku Ida, Darryl Restaino
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Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same
Publication number: 20060189153Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.Type: ApplicationFiled: April 19, 2006Publication date: August 24, 2006Applicant: International Business Machines CorporationInventors: Daniel Edelstein, Alfred Grill, Vishnubhai Patel, Darryl Restaino -
Publication number: 20060183345Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.Type: ApplicationFiled: February 16, 2005Publication date: August 17, 2006Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SONY CORPORATIONInventors: Son Nguyen, Sarah Lane, Jia Lee, Kensaku Ida, Darryl Restaino, Takeshi Nogami
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Publication number: 20060134911Abstract: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.Type: ApplicationFiled: December 22, 2004Publication date: June 22, 2006Inventors: Darryl Restaino, Donald Canaperi, Judith Rubino, Sean Smith, Richard Henry, James Fluegel, Mahadevaiyer Krishnan
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Publication number: 20050230831Abstract: An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.Type: ApplicationFiled: April 19, 2004Publication date: October 20, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence Clevenger, Stefanie Chiras, Timothy Dalton, James Demarest, Derren Dunn, Chester Dziobkowski, Philip Flaitz, Michael Lane, James Lloyd, Darryl Restaino, Thomas Shaw, Yun-Yu Wang, Chih-Chao Yang
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Process for removing impurities from low dielectric constant films disposed on semiconductor devices
Publication number: 20050087490Abstract: A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.Type: ApplicationFiled: October 28, 2003Publication date: April 28, 2005Applicant: International Business Machines CorporationInventors: Mark Chace, Jeffrey Hedrick, Habib Hichri, Keith Pope, Jia Lee, Kelly Malone, Kenneth McCullough, Wayne Moreau, Darryl Restaino, Shahab Siddiqui -
Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same
Publication number: 20050059258Abstract: A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition layer provides strong adhesion and cohesive strength between the first and third layers of the structure. Additionally, a semiconductor device structure and method for manufacture includes an insulating structure comprising a multitude of dielectric and conductive layers with respective transition bonding layers disposed to enhance interfacial strength among the different layers. Further, an electronic device structure incorporates layers of insulating and conductive materials as intralevel or interlevel dielectrics in a back-end-of-the-line (“BEOL”) wiring structure in which the interfacial strength between different pairs of dielectric films is enhanced by a thin intermediate transition bonding layer.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel Edelstein, Alfred Grill, Vishnubhai Patel, Darryl Restaino -
Publication number: 20050006242Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.Type: ApplicationFiled: July 10, 2003Publication date: January 13, 2005Applicant: International Business Machines CorporationInventors: Panayotis Andricacos, Dean Chung, Hariklia Deligianni, James Fluegel, Keith Kwietniak, Peter Locke, Darryl Restaino, Soon-Cheon Seo, Philippe Vereecken, Erick Walton
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Patent number: 6806182Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.Type: GrantFiled: May 1, 2002Date of Patent: October 19, 2004Assignees: International Business Machines Corporation, Infineon Technologies, AG, United Microelectronics Co.Inventors: Darryl Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, Chih-Chih Liu, Hsueh-Chung Chen, Tong-Yu Chen, Gwo-Shii Yang, Chiung-Sheng Hsiung
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Publication number: 20030207559Abstract: Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.Type: ApplicationFiled: May 1, 2002Publication date: November 6, 2003Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, Infineon Technologies North America Corp., United Microelectronics Co.Inventors: Darryl Restaino, Shahab Siddiqui, Erdem Kaltalioglu, Delores Bennett, C. C. Liu, Hsueh-Chung Chen, Tong-Yu Chen, Gwo-Shii Yang, Chiung-Sheng Hsiung
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Patent number: 6140236Abstract: A metal interconnect layer that fills in a via hole formed by first depositing a first Al--Cu film on the sidewalls of the via hole at a low temperature and a low sputtering power and then depositing a second Al--Cu film on the first Al--Cu film at a high temperature and high sputtering power. Sputtering is performed in two steps at low and high temperatures within the same sputtering chamber. The deposition at low temperature and low sputtering power provides good coverage in the via hole, and the deposition at high temperature and high sputtering power reduces the process time.Type: GrantFiled: April 21, 1998Date of Patent: October 31, 2000Assignees: Kabushiki Kaisha Toshiba, Siemens Microelectronics, Inc., International Business Machines CorporationInventors: Darryl Restaino, Chi-Hua Yang, Hans W. Poetzlberger, Tomio Katata, Hideaki Aochi
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Patent number: 5872694Abstract: Method and apparatus are provided for determining a warpage of a wafer (14) for providing a minimum clamping voltage to an electrostatic chuck (ESC) when the wafer is subsequently processed thereon. The apparatus includes an electrostatic chuck (12, 120) and a control arrangement (16, 18, 20). The electrostatic chuck includes a clamping surface (13, 130) for clamping a wafer thereto by a clamping force that is dependent on a clamping voltage applied to the electrostatic chuck. The control arrangement is used to detect an inherent warpage in the wafer prior to a processing of that wafer, and determine a minimum clamping voltage from the measured warpage that is to be applied to the electrostatic chuck during a subsequent processing of the wafer. The minimum clamping voltage has a value for each wafer that securely clamps the wafer to the clamping surface and avoids excessive warpage and backside abrasion of the wafer.Type: GrantFiled: December 23, 1997Date of Patent: February 16, 1999Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Mark Hoinkis, Darryl Restaino
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Patent number: 5798301Abstract: A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C.Type: GrantFiled: April 29, 1997Date of Patent: August 25, 1998Assignees: Siemens Aktiengesellschaft, International Business Machines CorporationInventors: Pei-Ing Paul Lee, Bernd Vollmer, Darryl Restaino, Bill Klaasen
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Patent number: 5641992Abstract: A multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in-situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures. The time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300.degree. C. and preferably between 350.degree. C.Type: GrantFiled: August 10, 1995Date of Patent: June 24, 1997Assignees: Siemens Components, Inc., International Business Machines CorporationInventors: Pei-Ing Paul Lee, Bernd Vollmer, Darryl Restaino, Bill Klaasen