Abstract: A non-volatile static random access memory includes: a static random access memory, a reading element and a first embedded non-volatile memory. The static random access memory includes a first inverter, a second inverter and two transistors, an output terminal of the first inverter and the input terminal of the second inverter are electrically connected to each other to serve as a Q node, an input terminal of the first inverter and an output terminal of the second inverter are electrically connected to each other to serve as a QB node, and the two transistors are electrically connected to the Q node and the QB node, respectively. The reading element is electrically connected to the Q node. The first embedded non-volatile memory is electrically connected to the QB node.

Abstract: A multi-gate ferroelectric memory comprises a fin-shaped channel layer, a front ferroelectric layer disposed on one side of the fin-shaped channel layer, a back ferroelectric layer disposed on another side of the fin-shaped channel layer, a front gate attached to the front ferroelectric layer and away from the fin-shaped channel layer, wherein the front gate is configured to connect a word line, and a back gate attached to the back ferroelectric layer and away from the fin-shaped channel layer, wherein the back gate is configured to connect a bit line. The present disclosure further discloses a memory array device, comprises a plurality of the multi-gate ferroelectric memories arranged as an array, a plurality of word lines and a plurality of bit lines.

Abstract: A multi-gate ferroelectric memory comprises a fin-shaped channel layer, a front ferroelectric layer disposed on one side of the fin-shaped channel layer, a back ferroelectric layer disposed on another side of the fin-shaped channel layer, a front gate attached to the front ferroelectric layer and away from the fin-shaped channel layer, wherein the front gate is configured to connect a word line, and a back gate attached to the back ferroelectric layer and away from the fin-shaped channel layer, wherein the back gate is configured to connect a bit line. The present disclosure further discloses a memory array device, comprises a plurality of the multi-gate ferroelectric memories arranged as an array, a plurality of word lines and a plurality of bit lines.

Abstract: The present disclosure relates to a flash memory having a plurality of control gates, including: a substrate. An oxide layer disposed on the substrate. A fin-shaped channel layer disposed on the oxide layer, and includes a first end portion, a second end portion, a top surface and two side surfaces, wherein the top surface and the two side surfaces are located between the first end portion and the second end portion, the top surface faces away from the oxide layer and separates the two sides. The two charge storage structures are respectively disposed on the two sides of the fin channel layer. The two gates are disposed on the oxide layer and respectively contact with the two charge storage structures. Two word conductive pillars are connected to the two gates respectively and extending from the two gates in a direction leaving the oxide layer.