Patents by Inventor Darshak Doshi
Darshak Doshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967954Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: April 23, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11923848Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: March 5, 2024Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11922105Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: November 10, 2021Date of Patent: March 5, 2024Assignee: Kepler Computing Inc.Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11861278Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: October 29, 2021Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11861279Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: January 19, 2022Date of Patent: January 2, 2024Assignee: KEPLER COMPUTING INC.Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11853666Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: October 15, 2021Date of Patent: December 26, 2023Assignee: KEPLER COMPUTING INC.Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11816408Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: September 17, 2021Date of Patent: November 14, 2023Assignee: KEPLER COMPUTING INC.Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11809801Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: October 8, 2021Date of Patent: November 7, 2023Assignee: KEPLER COMPUTING INC.Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya
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Patent number: 11757452Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: September 12, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11750197Abstract: A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.Type: GrantFiled: April 20, 2022Date of Patent: September 5, 2023Assignee: KEPLER COMPUTING INC.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Darshak Doshi, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 11748537Abstract: A computer-aided design (CAD) tool is provided for logic optimization and synthesis. The CAD tool executes a process that involves optimizing power, performance, and area (PPA) of a logic circuit by minimizing a number of CMOS gates, and majority and/or minority gates in the circuit and its depth. The CAD tool implements a methodology of optimizing logic synthesis based on a mix of standard cell libraries (such as AND, OR, NAND, NOR, XOR, Multiplexer, full adder, half adder, etc.) and varying input majority and minority gates (where the number of inputs in the minority and majority gates could vary as odd numbers from 3 and above). The standard cell libraries cells may contain minority and/or majority gates.Type: GrantFiled: July 23, 2021Date of Patent: September 5, 2023Inventors: Ikenna Odinaka, Sasikanth Manipatruni, Darshak Doshi, Rajeev Kumar Dokania, Amrita Mathuriya