Patents by Inventor Darshan Kobla
Darshan Kobla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10224115Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.Type: GrantFiled: May 8, 2017Date of Patent: March 5, 2019Assignee: Intel CorporationInventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
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Publication number: 20180005709Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.Type: ApplicationFiled: May 8, 2017Publication date: January 4, 2018Applicant: Intel CorporationInventors: Joon-Sung YANG, Darshan KOBLA, Liwei JU, David ZIMMERMAN
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Patent number: 9646720Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.Type: GrantFiled: July 29, 2015Date of Patent: May 9, 2017Assignee: Intel CorporationInventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
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Patent number: 9298573Abstract: A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.Type: GrantFiled: March 30, 2012Date of Patent: March 29, 2016Assignee: Intel CorporationInventors: Darshan Kobla, David Zimmerman, Vimal K. Natarajan
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Publication number: 20160055922Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.Type: ApplicationFiled: July 29, 2015Publication date: February 25, 2016Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
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Patent number: 9236143Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold programming values for the generic programmable address scrambler.Type: GrantFiled: December 28, 2011Date of Patent: January 12, 2016Assignee: Intel CorporationInventors: Darshan Kobla, David Zimmerman, Vimal Natarajan
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Patent number: 9190173Abstract: A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one or more memory layers; and a system element that is coupled with the memory stack. The system element includes a memory controller for the memory stack; a BIST circuit for testing of the memory stack; and a generic data scrambler for scrambling of data according to a data scrambling algorithm for the memory stack. The generic data scrambler includes a programmable lookup table to hold data factors for each possible outcome of the data scrambling algorithm, and the programmable lookup table is to generate a set of data factors based on addresses of data for testing of the memory stack.Type: GrantFiled: March 30, 2012Date of Patent: November 17, 2015Assignee: Intel CorporationInventors: Darshan Kobla, David Zimmerman, John C. Johnson, Vimal K. Natarajan
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Patent number: 9158619Abstract: An apparatus, system, and method provide for on chip redundancy repair for stacked memory devices. A memory device may include a memory stack including one or more layers of dynamic random-access memory (DRAM) and a system element coupled with the memory stack, the system element including a memory controller for control of the memory stack, and repair logic that is coupled with the memory controller. The repair logic is to hold repair addresses that are identified as failing addresses for defective areas of the memory stack, with the repair logic to receive a memory operation request and implement redundancy repair for an operation address for the request using a repair logic memory to store the repair addresses and data for the repair addresses.Type: GrantFiled: March 30, 2012Date of Patent: October 13, 2015Assignee: Intel CorporationInventors: Darshan Kobla, David J. Zimmerman, Vimal K. Natarajan
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Patent number: 9136021Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.Type: GrantFiled: December 23, 2011Date of Patent: September 15, 2015Assignee: Intel CorporationInventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
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Publication number: 20140237307Abstract: A generic address scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory stack having one or more of coupled memory elements, a built-in self-test circuit including a generic programmable address scrambler for the mapping of logical addresses to physical addresses for the memory elements, and one or more registers to hold pro-gramming values for the generic programmable address scrambler.Type: ApplicationFiled: December 28, 2011Publication date: August 21, 2014Inventors: Darshan Kobla, David Zimmerman, Vimal Natarajan
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Publication number: 20140164833Abstract: A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.Type: ApplicationFiled: March 30, 2012Publication date: June 12, 2014Inventors: Darshan Kobla, David Zimmerman, Vimal K. Natarajan
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Publication number: 20140013185Abstract: On chip redundancy repair for memory devices. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM. The system element includes a memory controller for control of the DRAM, and repair logic coupled with the memory controller, the repair logic to hold addresses identified as failing addresses for defective areas of the DRAM. The repair logic is configured to receive a memory operation request and to implement redundancy repair for an operation address for the request.Type: ApplicationFiled: March 30, 2012Publication date: January 9, 2014Inventors: Darshan Kobla, David J. Zimmerman, Vimal K. Natarajan
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Publication number: 20140013169Abstract: A generic data scrambler for a memory circuit test engine. An embodiment of a memory device includes a memory; a memory controller for the memory; a built-in self-test (BIST) circuit for the testing of the memory; and a generic data scrambler for scrambling of data according to a scrambling algorithm for the memory, where each algorithm is based on values of an address for data. The generic data scrambler includes a programmable lookup table to hold values for each possible outcome of the algorithm, the lookup table to generate a set of data factors, and a logic for combining the data with the data factors to generate scrambled data.Type: ApplicationFiled: March 30, 2012Publication date: January 9, 2014Inventors: Darshan Kobla, David Zimmerman, John C. Johnson, Vimal K. Natarajan
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Publication number: 20130294184Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.Type: ApplicationFiled: December 23, 2011Publication date: November 7, 2013Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman