Patents by Inventor Darshan Kumar Nandanwar

Darshan Kumar Nandanwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250103335
    Abstract: A processing unit including a dynamically allocatable vector register file for non-vector instruction processing is disclosed. The processing unit includes an integer execution circuit and integer register file for processing integer instructions. The processing unit also includes a vector execution circuit and a vector register file for processing vector instructions. The integer and vector register files are each sized at design time. A processing unit may be called upon to execute varying workloads that vary between integer and vector operations. Rather than statically dedicating the entire vector register file to vector registers, the processor is configured to dynamically allocate a portion(s) of the vector registers in the vector register file for use in the execution of integer instructions.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Inventors: Hithesh Hassan Lepaksha, Darshan Kumar Nandanwar, Sagar Bamashetti
  • Publication number: 20250103545
    Abstract: A method of execution unit (EU) sharing between processor cores is described. The method includes encountering a structural hazard associated with an issued instruction in an instruction queue of a dispatch stage inside an active processor core. The method also includes issuing a request for an idle execution unit of an inactive processor core. The method further includes sending a transaction containing source operands of the issued instruction, and a word address of a result buffer as a destination operand to an allocated EU of the inactive processor core. The method also includes replacing the issued instruction in the instruction queue with a load operation to forward a result of the issued instruction from the result buffer based on the word address.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 27, 2025
    Inventors: Hithesh Hassan LEPAKSHA, Sharath Kumar NAGILLA, Darshan Kumar NANDANWAR
  • Publication number: 20250087295
    Abstract: This disclosure provides systems, methods, and devices for memory systems that support SRAM fault correction. In a first aspect, a method includes receiving, by a memory controller coupled to a memory module through a first channel and configured to store data in and access data stored in the memory module through the first channel from a host device, data to be stored in a memory of the memory module, determining, by the memory controller, a row in the memory at which the data will be stored, determining, by the memory controller based on the row, an address associated with the row, wherein the address indicates one bit location in the row at which data will not be stored, and storing, by the memory controller, the data at the row in accordance with the address, wherein the data is not stored at the one bit location.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Inventors: Darshan Kumar Nandanwar, Kartik Gunvantbhai Desai, Raghava Rao M V
  • Publication number: 20240402772
    Abstract: A system for performing predictive run-time thermal mitigation in a processor uses at least a first temperature sensor and a first power sensor or meter to measure a junction temperature, TJUNC, value and power consumption, PTOTAL, value in the processor and predicts what a temperature, TEMPPRED, value of the processor will be in a later clock cycle of the processor based at least in part on the TJUNC and PTOTAL values. If the TEMPPRED value exceeds a preselected temperature threshold, THTEMP, value, one or more thermal mitigation actions are taken to ensure that a future TJUNC value measured n sample periods from the current sample period k of the processor will not exceed the THTEMP value.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Darshan Kumar NANDANWAR, Kartik Gunvantbhai DESAI, Raghava Rao MV
  • Publication number: 20240403216
    Abstract: Optimizing cache energy consumption in processor-based devices is disclosed herein. In some aspects, a processor-based device comprises a way lookup table (WLUT) circuit that is configured to receive an effective address (EA) for a memory access request. The WLUT circuit determines that a tag portion of the EA corresponds to a tag of a WLUT entry among a plurality of WLUT entries. In response, the WLUT circuit transmits a predicted way indicator of the WLUT entry to a cache controller. The cache controller accesses, in a set among a plurality of sets of a cache memory device corresponding to a set portion of the EA, only a predicted tag way among a plurality of tag ways of the cache memory device indicated by the predicted way indicator and only a predicted data way among a plurality of data ways of the cache memory device indicated by the predicted way indicator.
    Type: Application
    Filed: May 30, 2023
    Publication date: December 5, 2024
    Inventors: Darshan Kumar Nandanwar, Kartik Gunvantbhai Desai
  • Patent number: 12153924
    Abstract: A system for performing energy-efficient computing reduces the amount of data that is transferred between a processor and an external memory device. The processor and the external memory device are equipped with first and second near data processing control units (NCUs), respectively, that coordinate offloading of preselected subprocesses from the processor to a first processing circuit disposed on or near the external memory device. When the processor is performing one of these preselected processes, the first NCU transmits commands and memory addresses to the second NCU. The processing circuit on or near the memory device performs the subprocess or subprocesses and the result is forwarded by the second NCU to the first NCU, which forwards it to the processor to complete the process.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: November 26, 2024
    Assignee: QUALCOMM Incorporated
    Inventor: Darshan Kumar Nandanwar
  • Publication number: 20240361931
    Abstract: Systems and methods for reducing data movement when performing large-sized memory transactions in a memory hierarchy are provided. For certain preselected types of large-size memory transactions, such as memset and memcopy operations, for example, logic of the processor determines whether the type of memory transaction being queued is one of the preselected types for which alteration of the path of data movement is an option. Logic of the processor also determines whether the size of the memory block associated with the transaction is sufficiently large to warrant altering the path of data movement. If the type is one of the preselected types and the size of the memory block is sufficiently large, logic of the LLC controller selects an altered path for data movement that reduces data movement and performs the transaction using the altered path.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Inventors: Hithesh Hassan LEPAKSHA, Darshan Kumar NANDANWAR, Sharath Kumar NAGILLA
  • Publication number: 20240281250
    Abstract: A system for performing energy-efficient computing reduces the amount of data that is transferred between a processor and an external memory device. The processor and the external memory device are equipped with first and second near data processing control units (NCUs), respectively, that coordinate offloading of preselected subprocesses from the processor to a first processing circuit disposed on or near the external memory device. When the processor is performing one of these preselected processes, the first NCU transmits commands and memory addresses to the second NCU. The processing circuit on or near the memory device performs the subprocess or subprocesses and the result is forwarded by the second NCU to the first NCU, which forwards it to the processor to complete the process.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventor: Darshan Kumar NANDANWAR
  • Publication number: 20240272698
    Abstract: A system for performing thermal mitigation in a multi-core processor determines which processing core(s) of the processor is responsible for causing the temperature to rise to an undesired level and then performs one or more thermal mitigation steps only in the responsible core to avoid degrading performance of the other cores. The system monitors digital activity (DA) of the pipeline stages of the cores, determines when the DA of a processing stage has caused temperature to rise to a particular level and then reduces the DA of at least one processing stage of the responsible core in order to reduce temperature. The system can also take one or more other thermal mitigation steps based on monitored temperature values, such as reducing clock frequency or selecting a different V/F corner of the responsible core.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 15, 2024
    Inventor: Darshan Kumar NANDANWAR
  • Patent number: 11940914
    Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: March 26, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Hithesh Hassan Lepaksha, Sharath Kumar Nagilla, Darshan Kumar Nandanwar, Nirav Narendra Desai, Venkata Biswanath Devarasetty
  • Publication number: 20230401152
    Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 14, 2023
    Inventors: Hithesh Hassan LEPAKSHA, Sharath Kumar NAGILLA, Darshan Kumar NANDANWAR, Nirav Narendra DESAI, Venkata Biswanath DEVARASETTY
  • Publication number: 20230401156
    Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Hithesh Hassan LEPAKSHA, Sharath Kumar NAGILLA, Darshan Kumar NANDANWAR, Nirav Narendra DESAI, Venkata Biswanath DEVARASETTY
  • Patent number: 11836086
    Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: December 5, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Hithesh Hassan Lepaksha, Sharath Kumar Nagilla, Darshan Kumar Nandanwar, Nirav Narendra Desai, Venkata Biswanath Devarasetty