Abstract: Systems and techniques are provided for processing image data. A respective first value enclosed by a convolution kernel in each position of a plurality of positions of the convolution kernel along a row of the image data can be obtained and stored using a respective memory location associated with each position of the plurality of positions. Based on each respective first value, an accumulated value corresponding to a convolution output for each position of the plurality of positions can be updated. A plurality of second values enclosed by the convolution kernel in each position of the plurality of positions can be obtained. The plurality of second values includes a subset of the respective first values and an additional second value. A memory location used to store a first value not included in the plurality of second values can be updated to store the additional second value.

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.

Abstract: The present disclosure relates to a method of modifying a polysilicon layer, which includes the following steps. A polysilicon layer is provided. Nitrogen is incorporated into the polysilicon layer toward a predetermined depth. The polysilicon layer incorporated with nitrogen is etched, wherein after the nitrogenized polysilicon is removed, the formation of the remaining polysilicon layer is nearly indistinguishable from the formation of the polysilicon layer.