Patents by Inventor DARWIN FAN

DARWIN FAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES
    Publication number: 20180294272
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Application
    Filed: October 30, 2017
    Publication date: October 11, 2018
    Applicant: Intel Corporation
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices
    Patent number: 9847340
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 19, 2017
    Assignee: Intel Corporation
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • METHODS OF TUNNEL OXIDE LAYER FORMATION IN 3D NAND MEMORY STRUCTURES AND ASSOCIATED DEVICES
    Publication number: 20150279851
    Abstract: 3D NAND memory structures and related method are provided. In some embodiments such structures can include a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, an interpoly dielectric (IPD) layer disposed between the floating gate material and control gate material such that the IPD layer electrically isolates the control gate material from the floating gate material, and a tunnel dielectric material deposited on the floating gate material opposite the control gate material.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Inventors: Darwin Fan, Sateesh Koka, Gordon Haller, John Hopkins, Shyam Surthi, Anish Khandekar
  • METHOD OF MODIFYING POLYSILICON LAYER THROUGH NITROGEN INCORPORATION FOR ISOLATION STRUCTURE
    Publication number: 20150206789
    Abstract: The present disclosure relates to a method of modifying a polysilicon layer, which includes the following steps. A polysilicon layer is provided. Nitrogen is incorporated into the polysilicon layer toward a predetermined depth. The polysilicon layer incorporated with nitrogen is etched, wherein after the nitrogenized polysilicon is removed, the formation of the remaining polysilicon layer is nearly indistinguishable from the formation of the polysilicon layer.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: JONATHAN PAPPAS, GIORGIO MARIOTTINI, DARWIN FAN, HSIAO TING WU, CHENG SHUN CHEN