Patents by Inventor Darwin Franseda Fan

Darwin Franseda Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142909
    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
    Type: Application
    Filed: January 2, 2025
    Publication date: May 1, 2025
    Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan, Manuj Nahar
  • Patent number: 12224310
    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
    Type: Grant
    Filed: December 6, 2023
    Date of Patent: February 11, 2025
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan, Manuj Nahar
  • Publication number: 20240234482
    Abstract: A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.
    Type: Application
    Filed: October 19, 2022
    Publication date: July 11, 2024
    Inventors: Sanket S. Kelkar, Michael Mutch, Luca Fumagalli, Hisham Abdussamad Abbas, Brenda D. Kraus, Dojun Kim, Christopher W. Petz, Darwin Franseda Fan
  • Publication number: 20240164114
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Application
    Filed: November 29, 2023
    Publication date: May 16, 2024
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Publication number: 20240136391
    Abstract: A microelectronic device comprises an access device comprising a source region and a drain region spaced from the source region, an insulative material vertically adjacent to the access device, and a capacitor within the insulative material and in electrical communication with the access device. The capacitor comprises a material comprising silicon oxynitride or titanium silicon nitride over surfaces of the insulative material, a first electrode comprising titanium nitride on the material, a dielectric material over the first electrode, and a second electrode on the dielectric material. Related methods of forming the microelectronic device and an electronic system including the microelectronic devices are also described.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Sanket S. Kelkar, Michael Mutch, Luca Fumagalli, Hisham Abdussamad Abbas, Brenda D. Kraus, Dojun Kim, Christopher W. Petz, Darwin Franseda Fan
  • Publication number: 20240105766
    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
    Type: Application
    Filed: December 6, 2023
    Publication date: March 28, 2024
    Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan, Manuj Nahar
  • Patent number: 11923272
    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
  • Patent number: 11871582
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Patent number: 11862668
    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan, Manuj Nahar
  • Publication number: 20230006034
    Abstract: Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
    Type: Application
    Filed: July 2, 2021
    Publication date: January 5, 2023
    Inventors: Fatma Arzum Simsek-Ege, Masihhur R. Laskar, Nicholas R. Tapias, Darwin Franseda Fan
  • Publication number: 20220238417
    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
  • Publication number: 20220157837
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N, Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffrey B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Patent number: 11335626
    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
  • Publication number: 20220093617
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Publication number: 20220084906
    Abstract: Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.
    Type: Application
    Filed: September 15, 2020
    Publication date: March 17, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Zhuo Chen, Irina V. Vasilyeva, Darwin Franseda Fan, Kamal Kumar Muthukrishnan
  • Patent number: 11264395
    Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Vassil N. Antonov, Ashonita A. Chavan, Darwin Franseda Fan, Jeffery B. Hull, Anish A. Khandekar, Masihhur R. Laskar, Albert Liao, Xue-Feng Lin, Manuj Nahar, Irina V. Vasilyeva
  • Patent number: 10923593
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov, Darwin Franseda Fan, Ali Moballegh
  • Publication number: 20210043768
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov, Darwin Franseda Fan, Ali Moballegh
  • Patent number: 10886130
    Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Darwin Franseda Fan, Junting Liu-Norrod, Michael Mutch
  • Patent number: 10777561
    Abstract: Methods, apparatuses, and systems related to reduction of tapering on a sidewall of an opening are described. An example method includes forming a silicate material comprising a gradient borophosphosilicate glass (BPSG) stack on a semiconductor structure. The example method further includes etching a portion of the silicate material to form an opening within the silicate material having sidewalls, wherein the gradient BSPG stack comprises varying concentrations of boron and phosphorous to reduce tapering of the sidewalls in response to the etching.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Devesh Dadhich Shreeram, Sanjeev Sapra, Masihhur R. Laskar, Darwin Franseda Fan, Jerome A. Imonigie