Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Abstract: A method of coating a surface of a glass ribbon during a drawing process using atmospheric vapor deposition is provided. The method includes forming a glass ribbon in a viscoelastic state, desirably with a fusion draw. The glass ribbon is drawn in the viscoelastic state. The glass ribbon is cooled in the viscoelastic state into an elastic state. The glass ribbon is directed into an open end of a reactor. The reactor includes multiple channels. A first channel directs a first reactant gas, a second channel directs a second reactant gas and one or more third channels draw excess reactant, or purge it with inert gas flow, or both.

Abstract: Surface modification layers and associated heat treatments, that may be provided on a sheet, a carrier, or both, to control both room-temperature van der Waals (and/or hydrogen) bonding and high temperature covalent bonding between the thin sheet and carrier. The room-temperature bonding is controlled so as to be sufficient to hold the thin sheet and carrier together during vacuum processing, wet processing, and/or ultrasonic cleaning processing, for example. And at the same time, the high temperature covalent bonding is controlled so as to prevent a permanent bond between the thin sheet and carrier during high temperature processing, as well as maintain a sufficient bond to prevent delamination during high temperature processing.

Abstract: An organic thin film transistor comprising a first gate, a second gate, a semiconducting layer located between the first gate and second gate and configured to operate as a channel and a source electrode and a drain electrode connected to opposing sides of the semiconductor layer. The organic thin film transistor also comprises a first dielectric layer located between the first gate and the semiconducting layer in a direction of current flow through the semiconductor layer, the first dielectric layer comprising a polar elastomeric dielectric material that exhibits a double layer charging effect when a set voltage is applied to the first gate and a second dielectric layer located between the second gate and the semiconducting layer.

Abstract: Methods for making electronic devices on thin sheets bonded to carriers. A surface modification layer and associated heat treatments, may be provided on a sheet, a carrier, or both, to control both room-temperature van der Waals (and/or hydrogen) bonding and high temperature covalent bonding between the thin sheet and carrier during the electronic device processing. The room-temperature bonding is controlled so as to be sufficient to hold the thin sheet and carrier together during vacuum processing, wet processing, and/or ultrasonic cleaning processing, during the electronic device processing. And at the same time, the high temperature covalent bonding is controlled so as to prevent a permanent bond between the thin sheet and carrier during high temperature processing, during the electronic device processing, as well as maintain a sufficient bond to prevent delamination during high temperature processing.

Abstract: An organic thin film transistor comprising a first gate, a second gate, a semiconducting layer located between the first gate and second gate and configured to operate as a channel and a source electrode and a drain electrode connected to opposing sides of the semiconductor layer. The organic thin film transistor also comprises a first dielectric layer located between the first gate and the semiconducting layer in a direction of current flow through the semiconductor layer, the first dielectric layer comprising a polar elastomeric dielectric material that exhibits a double layer charging effect when a set voltage is applied to the first gate and a second dielectric layer located between the second gate and the semiconducting layer.

Abstract: Methods and articles are provide for: a substrate having first and second opposing surfaces; an intermediate layer substantially covering the first surface of the substrate, the intermediate layer being between about 1-5 microns in thickness and having a hardness of at least 15 GPa; a first outer layer substantially covering the intermediate layer; and a second outer layer substantially covering the first outer layer, and having a hardness of at least 15 GPa.

Abstract: A method of cleaning thin glass substrates comprises applying a sequence of chemical washing steps as the thin glass substrate is being conveyed in a conveyance direction. In addition, surfaces of the glass substrate may be treated to enhance electrostatic discharge properties of the glass substrates.

Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AlGaAs are also amenable to beneficial processes described herein.

Abstract: A thin sheet (20) disposed on a carrier (10) via a surface modification layer (30) to form an article (2), wherein the article may be subjected to high temperature processing, as in FEOL semiconductor processing, not outgas and have the thin sheet maintained on the carrier without separation therefrom during the processing, yet be separated therefrom upon room temperature peeling force that leaves the thinner one of the thin sheet and carrier intact. Interposers (56) having arrays (50) of vias (60) may be formed on the thin sheet, and devices (66) formed on the interposers. Alternatively, the thin sheet may be a substrate on which semiconductor circuits are formed during FEOL processing.

Abstract: A method of coating a surface of a glass ribbon during a drawing process using atmospheric vapor deposition is provided. The method includes forming a glass ribbon in a viscoelastic state, desirably with a fusion draw. The glass ribbon is drawn in the viscoelastic state. The glass ribbon is cooled in the viscoelastic state into an elastic state. The glass ribbon is directed into an open end of a reactor. The reactor includes multiple channels. A first channel directs a first reactant gas, a second channel directs a second reactant gas and one or more third channels draw excess reactant, or purge it with inert gas flow, or both.

Abstract: A method of cleaning thin glass substrates comprises applying a sequence of chemical washing steps as the thin glass substrate is being conveyed in a conveyance direction. In addition, surfaces of the glass substrate may be treated to enhance electrostatic discharge properties of the glass substrates.

Abstract: A method for pseudomorphic growth and integration of an in-situ doped, strain-compensated metastable compound base into an electronic device, such as, for example, a SiGe NPN HBT, by substitutional placement of strain-compensating atomic species. The invention also applies to strained layers in other electronic devices such as strained SiGe, Si in MOS applications, vertical thin film transistors (VTFT), and a variety of other electronic device types. Devices formed from compound semiconductors other than SiGe, such as, for example, GaAs, InP, and AtGaAs are also amenable to beneficial processes described herein.

Abstract: A method and system for providing a metal oxide semiconductor (MOS) device are described. The method and system include providing a source, a drain, and a channel residing between the source and the drain. At least a portion of the channel includes an alloy layer including an impurity having a graded concentration. The method and system also include providing a gate dielectric and a gate electrode. At least a portion of the gate dielectric resides above the alloy layer. The gate dielectric resides between the alloy layer and the gate electrode.

Abstract: Disclosed herein are devices, methods and systems for ex-situ component recovery. The ex-situ recovery can be performed by desorbing or outgassing components of a processing system in a recovery system, rather than in the processing system itself. The recovery system can include a docking station and/or a heated vacuum chamber. The heated vacuum chamber can be used to desorb or outgas components that will be located inside the processing system, while the docking station can be used to desorb or outgas components that will be connected to the processing system. The processing system components can be placed under pressure by the recovery system to desorb or outgas contaminants and remove virtual leaks. The recovery system pressure can include a vacuum roughing pump, a turbomolecular pump, and/or a cryogenic pump to apply a pressure necessary to desorb or outgas the components.

Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) is provided. The method includes providing a substrate including a collector region; forming a compound base region over the collector region; and forming an emitter region over the compound base region including forming a first emitter layer within the emitter region and doping the first emitter layer with a pre-determined percentage of at least one element associated with the compound base region. In one implementation, an emitter region is formed including multiple emitter layers to enhance a surface recombination surface area within the emitter region.

Abstract: A method and system for forming high-quality epitaxial films. In one embodiment, the method includes cleaning a substrate, reducing adsorbed moisture on the substrate in a predefined temperature and predefined oxygen level atmosphere, and removing native oxide from the substrate. The method also includes prebaking the substrate and growing an epitaxial layer doped with an impurity, wherein the impurity has a nano-impurity profile.

Abstract: A method and system for providing a bipolar transistor is described. The method and system include providing a compound base region, providing an emitter region coupled with the compound base region, and providing a collector region coupled with the compound base region. The bipolar transistor may also include at least one other predetermined portion. The method and system also include providing at least one predetermined amount of oxygen to at least one of the compound base region, the emitter region, the collector region, and the predetermined portion of the bipolar transistor.

Abstract: A method and system for providing an alloy layer in a semiconductor device are described. The method and system ramping a first gas including a first constituent of the alloy layer from a first level to a second level different from the first level while the alloy layer is grown. The method and system also include ramping a second gas including a second constituent of the alloy layer from a third level to a fourth level different from the third level while the alloy layer is grown. In one aspect, the alloy layer includes silicon and germanium. In this aspect, the first gas includes silicon, while the second gas includes germanium.

Abstract: A method and system for providing a semiconductor device is described. The method and system include providing a compound region and providing a doped region. The compound region includes an alloy having an impurity. The impurity has a graded profile in the compound region. The doped region includes a dopant having a profile. The profile includes a retrograde region. In one aspect, the semiconductor device is a bipolar transistor. In this aspect, the method and system include providing an emitter region, a collector region, and a compound base region. The compound base region resides between the emitter region and the collector region. The compound base region has a collector side and includes an alloy and a dopant having a profile. The profile includes a retrograde region residing on the collector side of the compound base region.