Abstract: Method and apparatus for enabling an XGA display adapter selectively to support VGA graphics mode virtualization during native mode operation of the adapter by rendering VGA graphics assist hardware and certain VGA registers accessible. In a preferred embodiment, the invention comprises an XGA display adapter which includes a host interface for interfacing the display adapter with a central processing unit (CPU) of a personal computer (PC), VGA graphics assist hardware for performing VGA graphics assist functions, a memory controller for reading and writing a video memory of the PC as requested by the CPU during video memory accesses, and a display interface for generating control and timing signals to a display of the PC. The XGA display adapter also includes a XGA Operating Mode Register having three control bits which can be written by applications software selectively to enable or disable the virtual VGA function of the present invention.

Abstract: Method and apparatus for adjusting the color of the sprite in display systems, so that the sprite is always distinctively visible irrespective of the underlying displayed data. A palette DAC of a display system is provided with sprite control logic, which derives the color of a sprite to be overlaid on an image displayed on a video display unit of a display system by inverting only the most significant bit (MSB) of each of the red, green and blue pixel data components of the underlying image. In a preferred embodiment, the sprite control logic circuit comprises first, second and third multiplexors (MUXes) each having a first input connected to receive the MSB of the red, green and blue pixel data components of the underlying image, respectively, and a second input connected to receive the output of first, second and third XOR gates, respectively.

Abstract: A method and means which upon detecting indicia embedded in a decoded run length coded bit string skips over a range of bit memory mapped addresses thus reducing the number of write operations into a counterpart bit mapped memory. The coded indicia include portions which specify a skip and a skip range for storage locations in said bit mapped memory.

Abstract: Method and apparatus for converting multibit pixel data to a lesser number of bit pixel data and re-expanding the compressed data. Luminance data for each pixel is established as the 5 most significant bits of the original luminance signal. The chrominance information for groups of pixels is subsampled, and a common chrominance value assigned to each of the pixels in a group. The resulting compressed pixels may be 8 bits wide providing economical possibilities to store the 8 bit wide data. The data is expanded for display by adding lower order data bits to the compressed luminance signal data bits. A subsampled chrominance data signal is appended to the expanded luminance data for display.

Abstract: An all points addressable raster scan graphics display system is operable in two modes. In the first mode, data is extracted from a refresh store, serialized, modified, and applied to a display device at a first frequency. In the second mode, data is extracted from the refresh store, serialized and partially modified at said first frequency, but it is then further modified and passed to the display device at an even sub harmonic, for example half, of the first frequency. The further modification includes concatenation of successive groups of display data bits. Accordingly, with the raster scan device operating at a constant scan velocity, the first mode provides a high picture element definition but relatively low color definition display, and the second mode provides a display with an even submultiple, for example half, the picture element definition but considerably greater color definition.

Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronizing signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or color definition modes in response to the polarity of one of the vertical or horizontal synchronizing signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a color signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The color converter, in response to the control signals, either passes color signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts color signals on four of the input lines to output signals on the six lines to the drive circuits.

Abstract: A raster scan display system includes a plurality of storage maps. These maps are addressable in either of two modes. In the first mode each map contains bit mapped data and the maps are addressed together to provide color signals from which color video signals are derived. In the second mode, one map contains character representing data and a further map, character display dot patterns. In this mode the first map is addressed to provide partial addresses for the further map. These partial addresses are combined with row scan data signals to access the further map from which the character display dot data is used to generate the video signals.

Abstract: A peripheral processing controller controls time-shared access to a memory by specialized peripheral devices. The specialized peripheral devices process data independently of a central processor that simply supervises the system. The peripheral processing controller uses predetermined modes of memory space allocation for the various peripheral devices. A memory address register in the controller is assigned to each peripheral device. In addition, each MAR has one or more predefined modes of memory space allocation and, when active, controls memory access for its assigned peripheral device. The modes also define the size of the block of space allocated and whether memory access scrolls through various blocks of space or jumps between blocks of space. The controller also detects when a peripheral device has consumed all the space in a block.

Abstract: The apparatus shown herein controls a facsimile system to reduce four source documents and print all four reduced copies on a single copy page. The facsimile system prints one of the source documents in each quadrant of the copy document. The images of the source documents are reduced in the horizontal dimension by discarding every other picture element in the scan image. The images are reduced in the vertical dimension by increasing the scanner speed so that the size of the picture element in the vertical dimension is doubled. At the receiver, two scanned and reduced images will be printed on the left-hand half of the copy document. Subsequently, two additional scanned and reduced images are printed on the right-hand half of the copy document. When printing the right-hand half of the copy document, the printer must be referenced to start printing at the horizontal mid-page of the copy document rather than the left-hand edge of the copy document.

Abstract: A digital display system includes a monitor arranged to receive digital display data and synchronizing signals to develop displays on a cathode ray tube. The monitor is switched between different line structure and/or color definition modes in response to the polarity of one of the vertical or horizontal synchronizing signals trains. A circuit receives this train to provide control signals to the horizontal time base and/or a color signal code converter. The time base control signal, in accordance with its binary value, controls the frequency of the time base. The color converter, in response to the control signals, either passes color signals received in parallel over six input lines without change to the cathode ray tube drive circuits or converts color signals on four of the input lines to output signals on the six lines to the drive circuits.