Patents by Inventor Daryl Bradley

Daryl Bradley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070255974
    Abstract: A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 1, 2007
    Applicant: ARM Limited
    Inventors: David Gilday, Daryl Bradley, Edmond Ashfield
  • Publication number: 20070170269
    Abstract: Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not communicating triggers modified behaviour. This can provide that the predetermined transaction protocol is not broken and/or complete a partially completed transaction when the domain concerned has recovered from an error or other event which disrupted the communication.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 26, 2007
    Applicant: ARM LIMITED
    Inventors: Sheldon Woodhouse, Richard Grisenthwaite, Daryl Bradley, Edmond Ashfield
  • Publication number: 20060049264
    Abstract: Within an integrated circuit 2 independently controllable domains 4, 6, 8, 10, 12, 14 may be unable to complete pending transactions taking place between domains. Each domain is provided with a transaction level state machine 20, 22 which is responsive to the state of the state machine within the other domain and when this indicates that the other domain is not capable of communicating triggers default behaviour ensuring that the predetermined transaction protocol is not broken.
    Type: Application
    Filed: January 31, 2005
    Publication date: March 9, 2006
    Applicant: ARM LIMITED
    Inventors: Daryl Bradley, Richard Grisenthwaite, Sheldon Woodhouse
  • Publication number: 20050210447
    Abstract: A trace data system is provided in which flush request signals are generated and passed to trace data sources to trigger them to output any buffered trace data they are storing which was generated prior to the flush request being signalled. When the trace data has been flushed from these trace data sources, they signal this by generating a flush complete signal. The flushing of trace data may advantageously be performed prior to a power-down operation and using a trace bus bridge.
    Type: Application
    Filed: March 16, 2004
    Publication date: September 22, 2005
    Inventors: Daryl Bradley, Andrew Swaine, Sheldon Woodhouse, John Horley
  • Publication number: 20050039078
    Abstract: A trace data formatter 30 assembles trace data frames 50. These trace data frames 50 include bytes which may either serve to carry a trace data source identifier ID or trace data. A system being traced has multiple trace data sources 12, 14, 16, 18 and when the trace data source which is generating the current trace data stream changes then a trace data source identifier ID is inserted within the trace data stream.
    Type: Application
    Filed: November 19, 2003
    Publication date: February 17, 2005
    Applicant: ARM LIMITED
    Inventors: Daryl Bradley, Sheldon Woodhouse, Andrew Swaine
  • Publication number: 20050033553
    Abstract: An integrated circuit is provided with multiple data processing components associated with respective sources which generate trace data streams. A reference timestamp generator is provided and the trace data streams are annotated such that they are output off-chip together with reference timestamp data. Outputting the reference timestamp data together with the trace data streams enables temporal correlation between points in different trace data streams by trace analysis tools.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 10, 2005
    Applicant: ARM LIMITED
    Inventors: Andrew Swaine, Daryl Bradley, Sheldon Woodhouse
  • Publication number: 20050034026
    Abstract: An integrated circuit 2 is provided with multiple sources 12, 14, 16, 18 of trace data streams that are input via respective dedicated trace buses 20, 24 to a trace data stream combiner 22, 26. The trace data bus has trace data signal lines ATDATA for carrying trace data signals and trace source identifying signal lines ATID for carrying trace source identifying signals. A trace data stream replicator 28 may be used to replicate a single trace data stream such that the resulting multiple trace data streams may be subject to different post-replication processing/filtering as desired.
    Type: Application
    Filed: August 7, 2003
    Publication date: February 10, 2005
    Applicant: ARM Limited
    Inventors: Andrew Swaine, Daryl Bradley, Sheldon Woodhouse