Abstract: Described is a computer system which is coupled to a remote computer via a network cable. The computer system has a normally closed enclosure and is capable of securing data retained within the system against unauthorized access and notifying the remote computer when an unauthorized access has occurred. The computer system includes an erasable memory element mounted within the enclosure for selective activation to active and inactive states and for receiving and storing a security password when in the active state. A manually operable option switch is mounted within the enclosure. The option switch is manually settable by a user of the computer system for setting the memory element to the active and inactive states.

Abstract: Disclosed is a computer system which can be powered on by at least a first and a second method wherein the first method is different from the second method. The computer system is operative to allow a user to select which one of at least two different pre-selected ordered lists of initial program load (IPL) devices are to be used depending on whether the system was powered on by the first method or the second method. The system includes a processor coupled to a local bus and an input/output (IO) bus. A non-volatile memory is coupled to the processor and the IO bus. The non-volatile memory has a basic input output system (BIOS) stored therein and the BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The non-volatile memory also stores a first pre-selected ordered list of IPL devices and a second pre-selected ordered list of IPL devices.

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs (Single In-line Memory Modules) that differ in size and speed of operation. The memory controller is operable, in response to an access request for a given SIMM, to read from a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS (Row Address Strobe) to CAS (Column Address Strobe) time, and CAS pulse width, depending on the SIMM being accessed.

Abstract: The present invention relates to a method and structure for implementing a 64/8 ECC algorithm on a SIMM using a computer which has a 32-bit bus and is configured with a 36-bit wide memory. This is accomplished by writing two successive 4 byte words from the system to latches, to form an 8 byte quad word, and writing 8 check bits utilizing the entire 64 bits of the quad word. One-half of the quad word (i.e., 32 bits) together with 4 of the 8 check bits for a total of 36 bits is stored at one address location in memory, and the remaining 32 bits of the quad word, together with the remaining 4 check bits, are stored at another, preferably the successive 36 bit, address location in memory. When the quad word and check bits are read from the memory, they are read serially, i.e.

Abstract: An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.