Patents by Inventor Daryl Sato

Daryl Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8299369
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: October 30, 2012
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
  • Patent number: 8056221
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: November 15, 2011
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
  • Patent number: 7797826
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: September 21, 2010
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
  • Publication number: 20100038127
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Application
    Filed: October 23, 2009
    Publication date: February 18, 2010
    Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
  • Patent number: 7583513
    Abstract: A device includes a plane metallization layer, and a plane plated through hole attached to the plane metallization layer and terminating at the at a major exterior surface with a plurality of component mounting pads. The plated through hole is attached to the plane metallization layer. The plane plated through hole is electrically isolated from the plurality of component mounting pads at the exterior surface. A method for testing the device includes contacting the signal carrying through hole, and contacting the plane through hole, and checking for current flow between the signal carrying through hole and the plane through hole. If current flows between the signal carrying through hole and the plane through hole the device fails. If no current flows between the signal carrying through hole and the plane through hole the device passes.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: David W Boggs, John H Dungan, Daryl A Sato
  • Patent number: 7385288
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Grant
    Filed: June 11, 2007
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Publication number: 20080029296
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 7, 2008
    Inventors: Gary Brist, Gary Long, Daryl Sato
  • Publication number: 20080029295
    Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 7, 2008
    Inventors: Gary Brist, Gary Long, Daryl Sato
  • Patent number: 7325303
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Publication number: 20070228562
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Application
    Filed: June 11, 2007
    Publication date: October 4, 2007
    Inventors: David Boggs, John Dungan, Frank Sanders, Daryl Sato, Dan Willis
  • Patent number: 7269899
    Abstract: A method for forming a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
  • Patent number: 7241680
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Publication number: 20070082512
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Application
    Filed: December 8, 2006
    Publication date: April 12, 2007
    Inventors: David Boggs, John Dungan, Frank Sanders, Daryl Sato, Dan Willis
  • Patent number: 7201583
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 10, 2007
    Assignee: Intel Corporation
    Inventors: David W. Boggs, John H. Dungan, Frank A. Sanders, Daryl A. Sato, Dan Willis
  • Patent number: 7147141
    Abstract: A method for providing an improved solder joint for a via-in-pad ball grid array package. One or more bonding pads are formed upon a substrate. One or more vias are formed through the substrate within the bonding pad. The vias are plugged with a via plug material. The via plug material is then preconditioned such that an amount of volatiles within the via plug material is reduced.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Daryl Sato, Gary Paek, John Dungan, David W. Boggs
  • Patent number: 7145243
    Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multi-layered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: December 5, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, Daryl A. Sato
  • Patent number: 7084354
    Abstract: An electronic assembly is disclosed. The electronic assembly includes a lower portion and a first elongate trace formed on an upper surface of the lower portion. The trace is covered by an upper portion, and an opening formed through an upper surface of the upper portion extends to the trace to expose a portion of the trace. A second elongate trace is formed on the upper portion. A portion of the second elongate trace positioned in the opening formed through the upper surface of the upper portion contacts the first elongate trace through the opening to form an electrical interconnection between the first trace and the second trace.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: August 1, 2006
    Assignee: Intel Corporation
    Inventors: David W. Boggs, Daryl A. Sato, John H. Dungan, Gary I. Paek
  • Patent number: 7064063
    Abstract: Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multilayered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, CO2 laser device, or other energy source.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: June 20, 2006
    Assignee: Intel Corporation
    Inventors: Gary A. Brist, Gary B. Long, Daryl A. Sato
  • Patent number: 7061116
    Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato
  • Patent number: 7061095
    Abstract: A printed circuit board and a system and method of embedding conductor channels into a printed circuit board. These conductor channels are used to provided increased power to circuits on the printed circuit board, provide shielding for these circuits and provide communications for these circuits. These conductor channels are created by ablating dielectric layers in the printed circuit board and depositing a conductive material therein.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: David W. Boggs, Rebecca Jessep, Carolyn McCormick, Daryl Sato