Abstract: A monolithic solid state power controller generally comprises a power supply, zero voltage crossing detector, operator interface circuitry, current sensing and trip timing logic (having zero current detection capability), drive circuitry, and a power switch. The current sensing and trip timing logic functions are implemented in a monolithic device which provides flexible mode of operation of the switch, operator command validation, status and mode indication, drive enablement in synchronization with zero voltage crossing of the source voltage, and tripout operation in synchronization with zero current crossing in the load current. Both fast trip (in response to catastrophic overcurrent) and timed trip (in response to overcurrent conditions occurring over a period of time) capabilities are provided.

Abstract: Any errors arising in a strobed MOS regenerative comparator error amplifier, such as off-set, characteristic changes due to radiation damage, and other circuit changes are corrected by comparing zero inputs for both the unknown and reference signal during a stabilization sample, storing any output signal present when the inputs are zero, in a D flip-flop, integrating the output signal from the D flip-flop and applying the integral back to the error amplifier to oppose the original unwanted error signal so that the output of the regenerative comparator will then be a logical true error signal depending only on the relative magnitude of the unknown and reference signals.

Abstract: A regulating digital power supply in which an error detector compares a reference signal voltage with an unknown loop signal voltage and upon being strobed the error detector outputs a signal depending upon the relative magnitude of the two input signals. This output signal controls the direction of count of an up/down counter that counts clock pulses. At appropriate intervals as controlled by the clock, the contents of the up/down counter are transferred to a down counter upon a command signal which also sets a flip-flop. When the down counter reaches zero and overflows it emits a signal that resets the flip-flop, the output thereof being a pulsewidth modulated regulated power supply. The flip-flop also controls a switch to a power source that is rectified and filtered and then fed back to the error detector comparator, thereby completing the loop.