Abstract: Parametric testing of an integrated circuit chip includes pressing first, second, and third contact elements (PRB-1,2,3) against first, second and third terminals (P1–3), respectively, of the integrated circuit and forcing first, second, and third reference currents (Iref) through first, second, and third circuit paths each including a corresponding ESD diode. Each path includes two of the contact elements, two associated contact resistances, and one of the ESD diodes. First, second, and third voltages (Vm1–3) are measured across the three circuit paths. Three equations representative of the three voltages are simultaneously solved to determine three contact resistances between the various contact elements and integrated circuit terminals. The voltages across the three contact resistances are computed by multiplying them by parametric test currents and are added to or subtracted from measured voltages of the contact elements to obtain accurate values of voltages of the integrated circuit terminals.