Patents by Inventor Das PURKAYASTHA
Das PURKAYASTHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150324300Abstract: A storage subsystem can achieve more efficient I/O processing by enabling users to specify and pass out of band I/O hints comprising an object to be hinted, a hint type, and caching strategies associated with a hint type. A hinted object may be either a virtual device or a file. In addition to priority cache, hint types may include never-cache, sticky-cache, and volatile-cache. Hints may be passed via command-line or graphical-user interfaces.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Applicant: LSI CORPORATIONInventors: Kishore Kaniyar Sampathkumar, Parag Maharana, Sumanesh Samanta, Saugata Das Purkayastha
-
Patent number: 9183128Abstract: The invention provides a method for controlling writing of data to a data storage card having a device controller and a storage medium. Particularly, the device controller receives a meta data synchronization disable command and in response, enters a first mode. In the first mode, the device controller does not synchronize meta data related to a data write request to write the data to the storage medium, leaving corresponding unsynchronized meta data. The device controller receives a data write request to write the data, and in response, effects the data write request such that the data is written to the storage medium. However, the meta data related to the data write request is not synchronized to the storage medium. Other aspects provide a corresponding device controller and software/firmware.Type: GrantFiled: February 23, 2012Date of Patent: November 10, 2015Assignee: ST-Ericsson SAInventor: Saugata Das Purkayastha
-
Publication number: 20150301956Abstract: In a data storage system in which a host system transfers data to a data storage controller having cache memory, the data storage controller can use a designated field of each of several cache data blocks, such as an application (APP) field, to contain protection information from fields of a host data block, such as the guard (GRD) and reference (REF) fields as well as the APP field.Type: ApplicationFiled: April 25, 2014Publication date: October 22, 2015Applicant: LSI CorporationInventor: Saugata Das Purkayastha
-
Publication number: 20150220452Abstract: Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the volatile RAM and reflected in page tables that reference the regions. The page tables are managed on a host computer executing the application. One region space in the volatile RAM is unused and available for transferred information. Mechanisms are provided for dynamically transferring regions and interfacing with the host computer. As the application sequentially accesses information in the stored regions, older regions are removed and new regions loaded from NVRAM to the volatile RAM.Type: ApplicationFiled: February 27, 2014Publication date: August 6, 2015Applicant: LSI CorporationInventors: Saugata Das Purkayastha, Luca Bert, Philip K. Wong, Anant Baderdinni
-
Publication number: 20150199269Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an input/output (I/O) operation directed to a file system. The controller may perform a read-fill based on a hint value when there is a read miss in the cache. The hint value may be based on the application access pattern. The hint value may be passed to a caching layer with a corresponding I/O.Type: ApplicationFiled: January 27, 2014Publication date: July 16, 2015Applicant: LSI CorporationInventors: Luca Bert, Anant Baderdinni, Saugata Das Purkayastha, Philip K. Wong
-
Publication number: 20150178201Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write followed by read condition on each of said cache windows and (ii) discarding data on the cache-lines associated with the cache windows after completion of the write followed by a read condition on the cache-lines.Type: ApplicationFiled: January 1, 2014Publication date: June 25, 2015Applicant: LSI CorporationInventors: Kishore Kaniyar Sampathkumar, Saugata Das Purkayastha, Parag R. Maharana
-
Publication number: 20150169458Abstract: An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state. The controller is connected to the memory and configured to (i) recognize sub-cache line boundaries and (ii) process the I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: LSI CorporationInventors: Saugata Das Purkayastha, Luca Bert, Horia Simionescu, Kishore Kaniyar Sampathkumar, Mark Ish
-
Publication number: 20150074355Abstract: An apparatus includes a memory and a controller. The memory may be configured to implement a cache and store meta-data. The cache generally comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines is associated with meta-data indicating one or more of a dirty state, an invalid state, and a partially dirty state. The controller is connected to the memory and may be configured to (i) detect an input/output (I/O) operation directed to a file system recovery log area, (ii) mark a corresponding I/O using a predefined hint value, and (iii) pass the corresponding I/O along with the predefined hint value to a caching layer.Type: ApplicationFiled: October 30, 2013Publication date: March 12, 2015Applicant: LSI CorporationInventors: Kishore Kaniyar Sampathkumar, Saugata Das Purkayastha
-
Publication number: 20140025906Abstract: The invention provides a method for controlling writing of data to a data storage card having a device controller and a storage medium. Particularly, the device controller receives a meta data synchronization disable command and in response, enters a first mode. In the first mode, the device controller does not synchronize meta data related to a data write request to write the data to the storage medium, leaving corresponding unsynchronized meta data. The device controller receives a data write request to write the data, and in response, effects the data write request such that the data is written to the storage medium. However, the meta data related to the data write request is not synchronized to the storage medium. Other aspects provide a corresponding device controller and software/firmware.Type: ApplicationFiled: February 23, 2012Publication date: January 23, 2014Applicant: ST-ERICSSON SAInventor: Saugata Das Purkayastha
-
Publication number: 20130326170Abstract: Exemplary embodiments provide for compressing, storing, retrieving and decompressing paged code from mass storage devices. By evaluating the size of compressed virtual pages relative to the storage page (read unit) of the mass storage device into which the compressed virtual pages are to be stored, decisions can be made which facilitate later read out and decompression of those compressed virtual pages. According to exemplary embodiments, a virtual page can be stored uncompressed, compressed but undivided or compressed and subdivided into a plurality of parts based on an evaluation.Type: ApplicationFiled: October 12, 2011Publication date: December 5, 2013Inventors: Vijaya Kumar Kilari, Saugata Das Purkayastha
-
Publication number: 20130254511Abstract: A memory management system for managing memory of a processing system having a primary memory and at least one secondary memory is disclosed. The memory is managed by optimizing the number of writes required by swapping one or more relevant pages of an application from the primary memory to the at least one secondary memory. The system comprises of a dynamic memory manager for allocating memory to the application from a memory pool and having a first table containing virtual addresses and chunk sizes of memory allocated by the application. The system further comprises of a swap manager having a second table containing the physical addresses of the primary memory pages and information whether the pages are allocated or not. The system further comprises of a memory management unit having a third table containing a mapping information of the physical addresses and the virtual addresses of the one or more physical pages used by the application and information whether the page is dirty or not.Type: ApplicationFiled: October 24, 2011Publication date: September 26, 2013Applicant: ST-Ericsson SAInventors: Saugata Das Purkayastha, Vijaya Kumar Kilari
-
Publication number: 20130205072Abstract: Methods for receiving data from a file system and storing it in a flash storage medium, wherein a bad block management process comprises queuing, at a bad block manager, one or more write requests, and receiving data associated with each of the one or more write requests and storing the received data in the bad block manager buffer; and performing cache management of data in the bad block manager buffer and subsequently returning a success status to the file system; and executing the one or more queued write requests in a separate task, wherein the executing comprises programming the received data to the flash storage medium during the bad block management process. Corresponding devices are also provided.Type: ApplicationFiled: June 1, 2011Publication date: August 8, 2013Applicant: ST-ERICSSON SAInventors: Mahesh Sreekandath, Saugata Das Purkayastha
-
Patent number: 7437568Abstract: Computer apparatus comprising a receiver for receiving an integrity metric for a computer entity via a trusted device associated with the computer entity, the integrity metric having values for a plurality of characteristics associated with the computer entity; a controller for assigning a trust level to the computer entity from a plurality of trust levels, wherein the assigned trust level is based upon the value of at least one of the characteristics of the received integrity metric.Type: GrantFiled: August 16, 2001Date of Patent: October 14, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Arindam Das-Purkayastha, Siani Lynne Pearson, Liqun Chen
-
Publication number: 20020026576Abstract: Computer apparatus comprising a receiver for receiving an integrity metric for a computer entity via a trusted device associated with the computer entity, the integrity metric having values for a plurality of characteristics associated with the computer entity; a controller for assigning a trust level to the computer entity from a plurality of trust levels, wherein the assigned trust level is based upon the value of at least one of the characteristics of the received integrity metric.Type: ApplicationFiled: August 16, 2001Publication date: February 28, 2002Applicant: Hewlett-Packard CompanyInventors: Arindam Das-Purkayastha, Siani Lynne Pearson, Liqun Chen