Patents by Inventor Das Sharma Debendra

Das Sharma Debendra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9317466
    Abstract: An apparatus and method are disclosed in which unrelated completion operations intended for a single destination (requestor) are coalesced to improve achievable data bandwidth. During transmission, the completion operations are collected and compressed into a single packet and transmitted along the link. At a receiving end of the link, the single packet is decompressed and the previously unrelated packets are returned to their initial state before receipt by the requestor. The method can be implemented in the root complex, end points, and/or switches, in the case of a PCIe implementation, but can also be applied to other protocols besides PCIe.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventor: Das Sharma Debendra
  • Publication number: 20150095544
    Abstract: An apparatus and method are disclosed in which unrelated completion operations intended for a single destination (requestor) are coalesced to improve achievable data bandwidth. During transmission, the completion operations are collected and compressed into a single packet and transmitted along the link. At a receiving end of the link, the single packet is decompressed and the previously unrelated packets are returned to their initial state before receipt by the requestor. The method can be implemented in the root complex, end points, and/or switches, in the case of a PCIe implementation, but can also be applied to other protocols besides PCIe.
    Type: Application
    Filed: December 9, 2014
    Publication date: April 2, 2015
    Inventor: DAS SHARMA DEBENDRA
  • Patent number: 8935453
    Abstract: An apparatus and method are disclosed in which unrelated completion operations intended for a single destination (requestor) are coalesced to improve achievable data bandwidth. During transmission, the completion operations are collected and compressed into a single packet and transmitted along the link. At a receiving end of the link, the single packet is decompressed and the previously unrelated packets are returned to their initial state before receipt by the requestor. The method can be implemented in the root complex, end points, and/or switches, in the case of a PCIe implementation, but can also be applied to other protocols besides PCIe.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventor: Das Sharma Debendra
  • Publication number: 20140281052
    Abstract: An apparatus and method are disclosed in which unrelated completion operations intended for a single destination (requestor) are coalesced to improve achievable data bandwidth. During transmission, the completion operations are collected and compressed into a single packet and transmitted along the link. At a receiving end of the link, the single packet is decompressed and the previously unrelated packets are returned to their initial state before receipt by the requestor. The method can be implemented in the root complex, end points, and/or switches, in the case of a PCIe implementation, but can also be applied to other protocols besides PCIe.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventor: Das Sharma Debendra