Abstract: Compositions are provided for formulations of ?-defensin and/or a ?-defensin analog that are highly suitable for parenteral administration. Such formulations provide the ?-defensin and/or a ?-defensin analog in a slightly acidic buffer that includes propylene glycol. Surprisingly, Inventors have found that such formulation increase bioavailability of a ?-defensin and/or a ?-defensin analog so provided by at least a factor of 10 relative to conventional isotonic saline solutions, and that such formulations dramatically improved bioavailability in human subjects relative to animal models. Inventors have also found that such formulations advantageously exhibit low viscosity at high peptide concentrations, reducing injection volume permitting sterilization by simple filtration.

Abstract: A method includes, by a computing system, receiving a querying image depicting a sampling area, processing the querying image using a single cluster detection model to identify one or more regions of the querying image depicting a cluster in the sampling area, processing the one or more regions using a cluster verification deep-learning model to determine whether each depicted cluster is a cell cluster, and determining that exactly one of the identified one or more regions depicts a cluster that is a cell cluster. The method further includes processing the region depicting the cell cluster using a morphology deep-learning model to determine that there is only one cell in the cell cluster and to determine that die morphology of the cell is acceptable.

Abstract: A method includes, by a computing system, receiving a querying image depicting a sampling area, processing the querying image using a single cluster detection model to identify one or more regions of the querying image depicting a cluster in the sampling area, processing the one or more regions using a cluster verification deep-learning model to determine whether each depicted cluster is a cell cluster, and determining that exactly one of the identified one or more regions depicts a cluster that is a cell cluster. The method further includes processing the region depicting the cell cluster using a morphology deep-learning model to determine that there is only one cell in the cell cluster and to determine that die morphology of the cell is acceptable.

Abstract: An apparatus for measuring vapor partial pressures of water and carbon dioxide includes a pair of infrared (IR) sources and a pair of quad filter detectors are placed opposite to one another such that the vapor partial pressures of water (H2O) and carbon dioxide (CO2) is measured and quantified in a short pathlength gas cell.

Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.

Abstract: An apparatus include one or more DACs and a resistor divider are configured to generate a variable bias voltage VBIAS with respect to a CM voltage VCM. The CM voltage VCM is applied to a cathode of one or more thermopiles or a negative input of one or more amplifiers to prevent saturation and over range of one or more low voltage readout amplifiers and one or more ADCs.

Abstract: Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.

Abstract: Compositions are provided for formulations of ?-defensin and/or a ?-defensin analog that are highly suitable for parenteral administration. Such formulations provide the ?-defensin and/or a ?-defensin analog in a slightly acidic buffer that includes propylene glycol. Surprisingly, Inventors have found that such formulation increase bioavailability of a ?-defensin and/or a ?-defensin analog so provided by at least a factor of 10 relative to conventional isotonic saline solutions, and that such formulations dramatically improved bioavailability in human subjects relative to animal models. Inventors have also found that such formulations advantageously exhibit low viscosity at high peptide concentrations, reducing injection volume permitting sterilization by simple filtration.

Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

Abstract: Consecutive logical block addresses (LBAs) are mapped to consecutive good blocks in a sequence of blocks in a memory device. For each bad block, a mapping process substitutes a next available good block. For a selected LBA, the mapping process determines a number X>1 of bad blocks before, and including, a corresponding block in the sequence, a number Y of bad blocks in the X blocks after the corresponding block in the sequence, and maps the LBA to a block which is X+Y blocks after the corresponding block, or, if the block which is X+Y blocks after the corresponding block is a bad block, to a next good block. The mapping technique can be used for a sequence of blocks in a trimmed die, where a bad block register stores physical block addresses of the trimmed away blocks.

Abstract: A memory management method includes identifying memory segments of a memory device. The method also includes identifying, for each memory segment, a number of faulty columns and determining a total number of faulty columns for the memory device. The method also includes, in response to a determination that the total number of faulty columns is greater than a threshold, identifying a memory segment having a highest number of faulty columns. The method also includes disabling the memory segment. Another method includes identifying, for each memory segment, a number of faulty memory blocks and determining a total number of faulty memory blocks. The method also includes, in response to a determination that the total number of faulty memory blocks is greater than a threshold, identifying a memory segment having a highest number of faulty memory blocks. The method also includes disabling the memory segment.

Abstract: An apparatus include one or more DACs and a resistor divider are configured to generate a variable bias voltage VBIAS with respect to a CM voltage VCM. The CM voltage VCM is applied to a cathode of one or more thermopiles or a negative input of one or more amplifiers to prevent saturation and over range of one or more low voltage readout amplifiers and one or more ADCs.

Abstract: Disclosed are methods of isolating and using a population of FOXP3+ regulatory T cells in a variety of preventative and therapeutic approaches to autoimmune diseases, graft-versus-host disease and transplant rejection.

Abstract: Disclosed are methods of isolating and using a population of FOXP3+ regulatory T cells in a variety of preventative and therapeutic approaches to autoimmune diseases, graft-versus-host disease and transplant rejection.

Abstract: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions.

Abstract: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions.

Abstract: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions.

Abstract: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions.

Abstract: The invention provides theta defensin analogs having antimicrobial activity. The invention also provides a method of reducing or inhibiting growth or survival of a microorganism in an environment capable of sustaining the growth or survival of the microorganism, comprising administering an effective amount of a theta defensin analog to the environment, thereby reducing or inhibiting the growth or survival of the microorganism.

Abstract: Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions.