Patents by Inventor Dattatreya B Nayak

Dattatreya B Nayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240086107
    Abstract: Technology is disclosed herein for handling of mixed random read and sequential read command sequences. Plane read commands are formed from one or more sequential read commands. A sequential read command may be split into multiple plane read commands at plane boundaries. The plane read commands are submitted to the respective planes as asynchronous independent plane read commands. Random read commands may be submitted to the planes as asynchronous independent plane read (AIPR) commands on par with the split sequential read commands. Therefore, AIPR may be used for both sequential read commands and random read commands. Submitting a split sequential read command to one or more planes while one or more other planes are performing a random read command can significantly improve performance.
    Type: Application
    Filed: September 12, 2022
    Publication date: March 14, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Dattatreya B Nayak, Ramanathan Muthiah
  • Patent number: 11923869
    Abstract: The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dattatreya B Nayak, Karthik N E, Noor Mohamed A A, Yunas Rashid
  • Publication number: 20230403030
    Abstract: The devices, methods, and apparatuses of the present disclosure address a lack of parallelism in a typical approach by eliminating the static mapping of the two or more low-density parity check (LDPC) engines to a plurality of flash controllers. The devices, methods, and apparatuses of the present disclosure include a dynamic LDPC mapping to the plurality of flash controllers.
    Type: Application
    Filed: June 14, 2022
    Publication date: December 14, 2023
    Inventors: Dattatreya B Nayak, Karthik N E, Noor Mohamed A A, Yunas Rashid