Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

Abstract: Presented herein are improvement to computer system architecture. In one embodiment, a method includes reconfiguring system interconnect links disposed between a first central processing unit socket and a second central processing unit socket, disposed together on a single motherboard, as peripheral bus links; and transmitting electrical signals, via the peripheral bus links, and via a printed circuit board that bridges the second central processing unit socket, to at least one input/output functional block that is disposed on the single motherboard and that is selectively connectable to the second central processing unit socket.

Abstract: A bridging device has at least two ports. The first port allows the device to communicate with devices on an expansion bus and at least one other port to allow the bridge to communicate with a system memory on a system bus or other devices on another expansion bus. The device is capable of identifying at least two regions in memory, a descriptor region and a data region. A descriptor provides information about segments of data in the data region. The bridge may detect descriptors read from the memory, extract information related to data associated with those descriptors and use this information to perform prefetching of data from the system memory.

Abstract: A bridging device has a first port to allow the device to communicate with other devices on an expansion bus and a second port to allow the device to communicate with devices on a second bus. The device also includes a memory to store data and a processor or logic to prefetch data upon request from a device on the expansion bus, tag any remaining prefetched data with an identifier upon a disconnecting event, and retain the prefetched data until a discarding event occurs. A method of controlling prefetch transactions on an expansion bus involves prefetching data across a primary bus for a device on a secondary bus. An indication that a disconnecting event has occurred is detected and any remaining prefetched data remaining is tagged with an identifier and retained. The data may be prefetched from a controlled prefetch region in the memory.