Abstract: The present invention provides a configurable architecture for serial communications. The architecture can emulate parallel to serial conversion devices for both synchronous and asynchronous data transmission. The invention uses a plurality of register sets to emulate standard interfaces. One register block performs data and control storage to communicate between a host computer and a local processor. A second register block emulates a serial communications controller (SCC) with its own data control storage and features to implement a number of communication protocols. The SCC provides serial data output. This invention provides an architecture of flexibility optimizing a configuration for synchronous and asynchronous requirements using the same basic blocks while still maintaining an interface compatible with standard requirements.

Abstract: A device for coupling a host computer to a serial communications device. A dual port register set is coupled to the CPU bus of a host computer. The dual port registers receive the control signals and data from the host computer. This information is immediately available to be read by a serial communications controller. In this invention, one channel of a two-channel serial communications controller is implemented to receive the parallel data and convert it to serial output. The parallel data is also provided directly to a microprocessor interface for use by a local microprocessor, if desired. The present invention eliminates unneeded conversion steps and reduces the amount of circuitry required to implement serial communications functions.