Abstract: A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.

Abstract: An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.

Abstract: An embodiment of a semiconductor device includes a III-nitride base structure of a first conductivity type, and a III-nitride emitter structure of a second conductivity type having a first surface and a second surface. The second surface is substantially opposite the first surface. The first surface of the III-nitride emitter structure is coupled to a surface of the III-nitride base structure. The semiconductor also includes a first dielectric layer coupled to the second surface of the III-nitride emitter structure, and a spacer coupled to a sidewall of the III-nitride emitter structure and the surface of the III-nitride base structure. The semiconductor also includes a base contact structure with a III-nitride material coupled to the spacer, the surface of the III-nitride base structure, and the first dielectric layer, such that the first dielectric layer and the spacer are disposed between the base contact structure and the III-nitride emitter structure.

Abstract: A gallium nitride (GaN)-based junction field-effect transistor (JFET) can include a GaN drain region having a top surface extending in a lateral dimension, a source region, and a GaN channel region of a first conductivity type coupled between the source region and the GaN drain region and operable to conduct electrical current between the source region and the GaN drain region. The JFET can also include a blocking layer disposed between the source region and the GaN drain region such that the GaN channel region is operable to conduct the electrical current substantially along the lateral dimension in a laterally-conductive region of the GaN channel region, and a GaN gate region of a second conductivity type coupled to the GaN channel region such that the laterally-conductive region of the GaN channel region is disposed between at least a portion of the blocking layer and the GaN gate region.

Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming one or more p-type regions in the n-type GaN epitaxial layer by using a first ion implantation. At least one of the one or more p-type regions includes an edge termination structure.

Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.

Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.