Abstract: A perforation apparatus particularly useful for creating perforations in a foam-in-bag cushion and methods of using such apparatus are provided. The perforation apparatus is comprised of a frame, a main shaft mounted in the frame so as to be rotatable about a central axis, at least one needle roller coupled to the main shaft such that rotation of the main shaft moves the needle roller through a predetermined arc of motion out of and into an operative position adjacent to and perforating a plastic film advancing past the needle roller, and an actuator coupled with the main shaft and operable to rotate the main shaft so as to move the needle roller. Optionally, the apparatus is further comprised of at least one backup roller. Methods of preparing and perforating a foam-in bag cushion using the perforating apparatus are also provided.

Abstract: A perforation apparatus particularly useful for creating perforations in a foam-in-bag cushion and methods of using such apparatus are provided. The perforation apparatus is comprised of a frame, a main shaft mounted in the frame so as to be rotatable about a central axis, at least one needle roller coupled to the main shaft such that rotation of the main shaft moves the needle roller through a predetermined arc of motion out of and into an operative position adjacent to and perforating a plastic film advancing past the needle roller, and an actuator coupled with the main shaft and operable to rotate the main shaft so as to move the needle roller. Optionally, the apparatus is further comprised of at least one backup roller. Methods of preparing and perforating a foam-in bag cushion using the perforating apparatus are also provided.

Abstract: The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.

Abstract: A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it.

Abstract: A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it.

Abstract: A computer bus that enables bus mastering agents to send/receive a burst of data to/from a slave agent without determining in advance the number of data words to be transferred, or even the maximum number of data words that could be transferred. Either the master, the slave, or the bus arbiter can terminate the burst at any time with minimum overhead. Furthermore, either the master or the slave can throttle the speed of the data transfer by adding wait states. Distributed address decode is performed by each agent coupled to the bus. Each agent must claim a transaction directed toward it by the master. If no agent claims the transaction within a predetermined number of clock periods, a subtractive decode device may claim the transaction by default. The bus also includes a bus lock wherein each bus slave agent may be able to enter a locked state, and once in the locked state, reject all accesses except those initiated by the master agent that locked it.