Patents by Inventor Dave Charles Stepniak
Dave Charles Stepniak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230040267Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: ApplicationFiled: October 5, 2022Publication date: February 9, 2023Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11482442Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: GrantFiled: February 24, 2021Date of Patent: October 25, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11469141Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: GrantFiled: August 7, 2018Date of Patent: October 11, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Patent number: 11171031Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.Type: GrantFiled: July 23, 2018Date of Patent: November 9, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano
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Publication number: 20210183683Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Inventors: Matthew John Sherbin, Michael Todd Wyant, Dave Charles Stepniak, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Publication number: 20200075386Abstract: A subring for holding tape connected to semiconductor dies and spanning a passage in a frame having a first diameter includes a base. An opening extends through the base and has a second diameter at least as large as the first diameter. A projection extends from the base to ends positioned on opposite sides of the base. The projection is adapted to clamp the tape to the frame and adapted to prevent relative movement between the tape, the subring, and the frame.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, SADA HIROYUKI, SHOICHI IRIGUCHI, GENKI YANO
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Publication number: 20200051860Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.Type: ApplicationFiled: August 7, 2018Publication date: February 13, 2020Inventors: Michael Todd Wyant, Dave Charles Stepniak, Matthew John Sherbin, Sada Hiroyuki, Shoichi Iriguchi, Genki Yano
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Publication number: 20200027772Abstract: A die matrix expander includes a subring including ?3 pieces, and a wafer frame supporting a dicing tape having an indentation for receiving pieces of the subring. The subring prior to expansion sits below a level of the wafer frame and has an outer diameter <an inner diameter of the wafer frame. A translation guide coupled to the subring driven by mechanical force applier moves the subring pieces in an angled path upwards and outwards for stretching the dicing tape including to a top most stretched position above the wafer frame that is over or outside the wafer frame. A cap placed on the pieces of the subring after being fully expanded over the dicing tape locks the dicing tape in the top most stretched position and secures the pieces of the expanded subring in place including when within the indentation during an additional expansion during a subsequent die pick operation.Type: ApplicationFiled: July 23, 2018Publication date: January 23, 2020Inventors: MATTHEW JOHN SHERBIN, MICHAEL TODD WYANT, DAVE CHARLES STEPNIAK, HIROYUKI SADA, SHOICHI IRIGUCHI, GENKI YANO
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Patent number: 6445069Abstract: A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.Type: GrantFiled: January 22, 2001Date of Patent: September 3, 2002Assignee: Flip Chip Technologies, L.L.C.Inventors: Jamin Ling, Dave Charles Stepniak
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Publication number: 20020096765Abstract: A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.Type: ApplicationFiled: January 22, 2001Publication date: July 25, 2002Inventors: Jamin Ling, Dave Charles Stepniak