Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.

Abstract: According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described.

Abstract: A media controller is reconfigurable to handle different formats and types of data. In one embodiment, the invention includes a media access controller coupled to a higher layer to exchange data with the higher layer, a physical layer connector coupled to the media access controller to exchange data with the media access controller and having an external physical interface to exchange data with an external device, and a configuration block to reconfigure the media access controller based on the format of the data of the external device.

Abstract: According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described.

Abstract: A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.

Abstract: In some embodiments, a frequency dependent gain circuit is coupled to an output of an amplifier. The gain circuit provides at least two ranges of frequency dependent gain characteristics in response to the output of the amplifier. A control circuit provides one of the at feast two gain values as an output. Other embodiments are described and claimed.

Abstract: A media controller is reconfigurable to handle different formats and types of data. In one embodiment, the invention includes a media access controller coupled to a higher layer to exchange data with the higher layer, a physical layer connector coupled to the media access controller to exchange data with the media access controller and having an external physical interface to exchange data with an external device, and a configuration block to reconfigure the media access controller based on the format of the data of the external device.

Abstract: An apparatus and method to improve bandwidth and reduce phase error in a tracking receiver is presented. According to one embodiment, an apparatus is presented comprising a phase comparator to generate indications based on a phase of a local clock signal and transitions in a stream of received data, an electoral loop filter to generate a phase shift signal based on the indications received from the phase comparator in a time interval, and a local clock controller to adjust the local clock signal based on the signal asserted from the electoral loop filter. The phase shift signal is either a phase increment signal or a phase decrement signal that is issued according to the majority of either increment indications or decrement indications received during the time interval.

Abstract: In some embodiments, a frequency dependent gain circuit is coupled to an output of an amplifier. The gain circuit provides at least two ranges of frequency dependent gain characteristics in response to the output of the amplifier. A control circuit provides one of the at feast two gain values as an output. Other embodiments are described and claimed.

Abstract: A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.

Abstract: A method and apparatus providing for high speed data transfers between a sending component and a receiving component is disclosed. In accordance with the present invention, in addition to handshake logic, the receiving component incorporates means for temporarily storing data words sent to the receiving component. The sending component incorporates, in addition to handshake logic, means for determining whether the aforementioned means for temporarily storing data is full, and therefore, unable to accept additional data. The sending component streams data words to the receiving component without the need for an acknowledge signal until it determines that the means for temporarily storing data is full. Asynchronous with this streaming of data words, whenever the receiving component reads a data word from the means for temporarily storing data, it sends an acknowledge signal to the sending component.

Abstract: A hose assembly suited for delivering viscous material to a dispenser nozzle at a controlled viscosity and temperature. The hose assembly includes a jacketed hose including an outer hose positioned around an inner hose carrying the mastic and defining an annular passage between the inner hose and the outer hose, and a hose cover assembly adapted to be releasably wrapped around a further remote hose carrying the mastic. The cover assembly includes an elongated strip of flexible material including generally parallel opposite longitudinal edges; a plurality of tubes embedded in the strip and running longitudinally through the strip; and coacting interengagable quick release means (such as a zipper) on the opposite longitudinal edges of the strip to enable the strip to be wrapped around the hose and secured in position around the hose by releasable interengagement of the quick release means.

Abstract: A method and apparatus providing for data broadcasting in a two dimensional mesh of processor nodes is disclosed. In accordance with the present invention, a self-timed message routing chip is coupled to each processor node, thereby forming a two dimensional mesh of message routing chips. Broadcasting originates from a corner node, and data can broadcast through the mesh routing chips to a row, a column, or a matrix of nodes. The mesh routing chips, together, form a self-timed pipeline with each individual message routing chip having broadcasting hardware which provides for the forking of a message within that particular message routing chip. The self-timed forking of a message within individual message routing chips directly supports data broadcasting within the two dimensional mesh.

Abstract: A temperature control system for an adhesive application system in which adhesive is delivered from a pump to a nozzle for application in bead form to a part. The control system includes a hose assembly extending from the pump to the nozzle and including an inner hose for carrying the adhesive and an outer hose defining an annular space between the outer hose and the inner hose for passage of water in a direction opposite to the direction of flow of the adhesive; a water conditioner selectively heating and cooling the water; and a controller receiving a reference signal representing a desired temperature of the adhesive at the nozzle and an actual adhesive temperature signal provided by a temperature sensor sensing the temperature of the adhesive being delivered to the nozzle and operative to compare the signals and generate appropriate signals for control of the water conditioner in a sense to maintain the desired water temperature and thereby the desired adhesive temperature.