Patents by Inventor Dave Ebsen

Dave Ebsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONFIGURING ERASE BLOCKS COUPLED TO A SAME STRING AS ZONES
    Publication number: 20240311036
    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. The first erase block can be configured as a first zone of one or more zones corresponding to a namespace independently of the second erase block.
    Type: Application
    Filed: March 15, 2024
    Publication date: September 19, 2024
    Inventors: Daniel J. Hubbard, Kishore K. Muchherla, Dave Ebsen, Akira Goda
  • MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL
    Publication number: 20240231617
    Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
    Type: Application
    Filed: March 21, 2024
    Publication date: July 11, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
  • Memory device programming technique for increased bits per cell
    Patent number: 11960722
    Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
  • MEMORY DEVICE PROGRAMMING TECHNIQUE FOR INCREASED BITS PER CELL
    Publication number: 20240028200
    Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Tomoharu Tanaka, Huai-Yuan Tseng, Dung V. Nguyen, Kishore Kumar Muchherla, Eric N. Lee, Akira Goda, James Fitzpatrick, Dave Ebsen
  • Method, apparatus and program storage device for providing control to a networked storage architecture
    Patent number: 7702757
    Abstract: A method, apparatus and program storage device for providing control to a networked storage architecture is disclosed. A networked storage device is provided. Controllers are coupled to the at least one networked storage device for controlling input/output operations of the networked storage device. The networked storage device includes a file system for storing data provided by a first of the controllers for retrieval by the other controllers.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: April 20, 2010
    Assignee: Xiotech Corporation
    Inventors: Lyle Bergman, Dave Ebsen, Randal S. Rysavy, Timothy W. Swatosh, Jeffrey L. Williams
  • Method, apparatus and program storage device for providing control to a networked storage architecture
    Publication number: 20050234916
    Abstract: A method, apparatus and program storage device for providing control to a networked storage architecture is disclosed. A networked storage device is provided. Controllers are coupled to the at least one networked storage device for controlling input/output operations of the networked storage device. The networked storage device includes a file system for storing data provided by a first of the controllers for retrieval by the other controllers.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 20, 2005
    Inventors: Lyle Bergman, Dave Ebsen, Randal Rysavy, Timothy Swatosh, Jeffrey Williams