Abstract: In various embodiments, a fuel injector may comprise a fuel nozzle and a pilot stage. The fuel nozzle may define a main fuel channel, a secondary fuel channel, a simplex fuel channel and a heat shield area. The main fuel channel may be disposed about at least a portion of the simplex fuel channel. The secondary fuel channel may be disposed about at least a portion of the simplex fuel channel. The heat shield area may be configured to separate and protect the fuel channels from a heat load to prevent fuel coking. The pilot stage may be operatively coupled to the fuel nozzle and may be configured to receive fuel from the secondary fuel channel or the simplex fuel channel. The main stage may be operatively coupled to the fuel nozzle. The main stage may be configured to receive fuel from the main fuel channel.

Abstract: In various embodiments, a fuel injector may comprise a fuel nozzle and a pilot stage. The fuel nozzle may define a main fuel channel, a secondary fuel channel, a simplex fuel channel and a heat shield area. The main fuel channel may be disposed about at least a portion of the simplex fuel channel. The secondary fuel channel may be disposed about at least a portion of the simplex fuel channel. The heat shield area may be configured to separate and protect the fuel channels from a heat load to prevent fuel coking. The pilot stage may be operatively coupled to the fuel nozzle and may be configured to receive fuel from the secondary fuel channel or the simplex fuel channel. The main stage may be operatively coupled to the fuel nozzle. The main stage may be configured to receive fuel from the main fuel channel.

Abstract: The present invention provides a method for use with program overlays, wherein code segments, along with data segments pertaining to the code segments, are transferred into a receiving memory segment. Program code is separated into common code and overlay code. The overlay code is then broken down into segments according to functionality, and the need to create segments that will fit into a receiving memory segment. An overlay control file is created for each segment, then a wrapper file. Linker command files are created for the common area and code area. The wrapper files and linker command files are used to create a common image file for the code/data. The common image is used to produce overlay sections, which are then concatenated together into one file. This one file is then loaded into memory for transfer of the overlays to a receiving memory area.

Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.

Abstract: The present invention provides a method for use with program overlays, wherein code segments, along with data segments pertaining to the code segments, are transferred into a receiving memory segment. Program code is separated into common code and overlay code. The overlay code is then broken down into segments according to functionality, and the need to create segments that will fit into a receiving memory segment. An overlay control file is created for each segment, then a wrapper file. Linker command files are created for the common area and code area. The wrapper files and linker command files are used to create a common image file for the code/data. The common image is used to produce overlay sections, which are then concatenated together into one file. This one file is then loaded into memory for transfer of the overlays to a receiving memory area.

Abstract: A raster image processing system (20) for producing the appropriate number and set of halftoned color separations for a select output device (24) is disclosed. The raster image processing system (20) includes a processing unit (30), an interpreter (32) and a color combiner (34). The interpreter (32) and color combiner (34) are application processes that are controlled by software running on the processing unit (30). The processing unit (30) identifies the number and set of colorants used to describe input image data and the number and set of halftoned color separations that a select output imaging device (24) is capable of rendering. The interpreter (32) converts the input data describing an image that is composed of “N” colorants into “N” halftoned color separations. The color combiner (34) thereafter converts the N halftoned color separations into “M” halftoned color separations that are ideally suited for the particular output device (24) chosen by a user of the system.

Abstract: The present invention provides an apparatus and method to reduce the memory footprint of a processor architecture by structuring processor code to be stored in an external device, and transferring into the processor certain code and associated data as it is needed. The processor code or algorithm is divided into a controlling piece and a working piece. The controlling piece can be located on a low-MIPS, high memory-footprint device, whereas the working piece can be located on a high-MIPS, low memory-footprint device. The working piece can also be broken down into phases or segments, which are put in a data store. The segments are then transferred, on an as-needed basis along with associated data, from the store into the constrained memory of the low memory-footprint device. Transfer is facilitated by a segment manager which can be processed from the low-MIPS device, or alternatively from the high-MIPS device.

Abstract: An active isolation device and method reduces the transmission of vibrations from interconnected elements. The device maintains a high stiffness between interconnected elements while actively reducing the transmission of relative movements, such as vibration. In one embodiment, the device uses accelerometers to measure the vibrations experienced by each of the interconnected elements and selectively operates an actuator between the two elements to maintain the position of one of the elements. In another embodiment, plural of the devices are used cooperatively to reduce the vibrations that would otherwise be transmitted from one element to a platform, permitting simultaneous control of multiple degrees of freedom of movement.

Abstract: A high precision linear actuator for compensating short stroke, high frequency vibrations in a space deployed structure comprises a set of cylindrical magnetic pole pieces affixed to respective ones of a pair of graphite flexures, that are mounted to a thermally conductive cylindrical housing, which is to be affixed to the space deployed structure. Reaction against the "proof mass" pole pieces is achieved by a magnetic field produced by set of stationary magnetic coils that surround the pole pieces and are energized by a vibration compensation reaction current supplied from a sense/control processor. Coaxial with and mounted integrally with the cylindrical pole pieces of the proof mass is an internal accelerater, which generates an output signal representative of the force to which the proof mass is subjected.