Patents by Inventor Dave J. McElroy

Dave J. McElroy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell array having continuous-strip field-oxide regions
    Patent number: 5469383
    Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: November 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Dave J. McElroy, Manzur Gill, Pradeep L. Shah
  • MOSFET cell array
    Patent number: 5365082
    Abstract: A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: November 15, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, Pradeep L. Shah, Dave J. McElroy
  • CMOS memory cell array
    Patent number: 5350706
    Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: September 27, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Dave J. McElroy, Manzur Gill, Pradeep L. Shah