Patents by Inventor Dave Minturn
Dave Minturn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11238203Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.Type: GrantFiled: June 30, 2017Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Rameshkumar Illikkal, Ananth Sankaranarayanan, David Zimmerman, Pratik M. Marolia, Suchit Subhaschandra, Dave Minturn
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Patent number: 10817176Abstract: Embodiments of the present disclosure may relate to a compute offload controller that may include a parser to parse a received compute offload command, and identify a block-based compute descriptor based at least in part on the compute offload command. In some embodiments, the compute offload controller may further include an offload executor to perform an operation on data in a block-based storage device based at least in part on the block-based compute descriptor. In some embodiments, the block-based compute descriptor may include a virtual input object, a virtual output object, and a compute type identifier. Other embodiments may be described and/or claimed.Type: GrantFiled: June 18, 2018Date of Patent: October 27, 2020Assignee: Intel CorporationInventors: Ian F. Adams, John Keys, Michael P. Mesnier, Dave Minturn
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Publication number: 20200328973Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: May 10, 2020Publication date: October 15, 2020Applicant: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 10652147Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: GrantFiled: December 29, 2017Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20190042093Abstract: Embodiments of the present disclosure may relate to a compute offload controller that may include a parser to parse a received compute offload command, and identify a block-based compute descriptor based at least in part on the compute offload command. In some embodiments, the compute offload controller may further include an offload executor to perform an operation on data in a block-based storage device based at least in part on the block-based compute descriptor. In some embodiments, the block-based compute descriptor may include a virtual input object, a virtual output object, and a compute type identifier. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 18, 2018Publication date: February 7, 2019Inventors: Ian F. Adams, John Keys, Michael P. Mesnier, Dave Minturn
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Publication number: 20190005176Abstract: Aspects of the embodiments are directed to systems, devices, and methods for accessing storage-as-memory. Embodiments include a microprocessor including a microprocessor system agent and a field programmable gate array (FPGA). The FPGA including an FPGA system agent to process memory access requests received from the microprocessor system agent across a communications link; a memory controller communicatively coupled to the system agent; and a high speed serial interface to link the system agent with a storage system. Embodiments can also include a storage device connected to the FPGA by the high speed serial interface.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Applicant: Intel CorporationInventors: Rameshkumar Illikkal, Ananth Sankaranarayanan, David Zimmerman, Pratik M. Marolia, Suchit Subhaschandra, Dave Minturn
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Publication number: 20180198709Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: December 29, 2017Publication date: July 12, 2018Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20170048142Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 9485178Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: GrantFiled: March 28, 2014Date of Patent: November 1, 2016Assignee: Intel CorporationInventors: Srihari Makikeni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20140211804Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: March 28, 2014Publication date: July 31, 2014Inventors: Srihari Makikeni, Ravi lyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 8036246Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: GrantFiled: September 30, 2009Date of Patent: October 11, 2011Assignee: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20110090920Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: December 29, 2010Publication date: April 21, 2011Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20100020819Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: September 30, 2009Publication date: January 28, 2010Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 7620071Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: GrantFiled: November 16, 2004Date of Patent: November 17, 2009Assignee: Intel CorporationInventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Patent number: 7581042Abstract: The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.Type: GrantFiled: December 29, 2004Date of Patent: August 25, 2009Assignee: Intel CorporationInventors: Dave Minturn, James B. Crossland, Sujoy Sen, Greg Cummings
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Publication number: 20060143333Abstract: The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.Type: ApplicationFiled: December 29, 2004Publication date: June 29, 2006Inventors: Dave Minturn, James Crossland, Sujoy Sen, Greg Cummings
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Publication number: 20060104303Abstract: In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.Type: ApplicationFiled: November 16, 2004Publication date: May 18, 2006Inventors: Srihari Makineni, Ravi Iyer, Dave Minturn, Sujoy Sen, Donald Newell, Li Zhao
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Publication number: 20050144422Abstract: A virtual to physical address translator in which a requesting process supplements a virtual memory address with a shortcut to a physical address associated with one level of a multi-level virtual address translation table. A second process, such as an I/O process, receives the shortcut and the virtual address and uses an address translator to determine the physical address. In some implementations, the shortcut may be made opaque to the requesting process such that the requesting process cannot determine the physical address represented in the shortcut.Type: ApplicationFiled: December 30, 2003Publication date: June 30, 2005Inventors: Gary McAlpine, Dave Minturn, Greg Regnier, Frank Berry
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Publication number: 20050138622Abstract: A method and apparatus for handling multiple processing streams in parallel on a single thread of a processing device. In one embodiment, a parallel processing agent includes a scheduler that multiplexes a number of processing streams, or pipelines, on a single thread of execution.Type: ApplicationFiled: December 18, 2003Publication date: June 23, 2005Inventors: Gary McAlpine, Dave Minturn
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Publication number: 20050058147Abstract: A data network and a method for providing prioritized data movement between endpoints connected by multiple logical channels. Such a data network may include a first node comprising a first plurality of first-in, first-out (FIFO) queues arranged for high priority to low priority data movement operations; and a second node operatively connected to the first node by multiple control and data channels, and comprising a second plurality of FIFO queues arranged in correspondence with the first plurality of FIFO queues for high priority to low priority data movement operations via the multiple control and data channels; wherein an I/O transaction is accomplished by one or more control channels and data channels created between the first node and the second node for moving commands and data for the I/O transaction during the data movement operations, in the order from high priority to low priority.Type: ApplicationFiled: October 27, 2004Publication date: March 17, 2005Inventors: Greg Regnier, Jeffrey Butler, Dave Minturn