Abstract: A receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. In the described embodiments, a token identifier is an integer value that acts as an index into a token array, which identifies the memory location.

Abstract: A buffer availability manager ensures that buffers are available before processes write thereto. The buffer availability manager maintains a plurality of register sets corresponding to the plurality of buffers. Each register set comprises a status indicator and a generation counter. Prior to writing to a buffer, the corresponding register set is read. Data is written to an individual buffer only if the status indicator indicates that the buffer is not busy, and the current value of the generation counter is not equal to a stored value from a prior register set read. The buffer availability manager detects writing of data to the buffer, and in response updates the status indicator to indicate that the buffer is busy. After processing the data in the buffer, the buffer availability manager updates the status indicator to not busy, and updates the value of the generation counter.

Abstract: Validation of various portions of received data, including validating a cut-through checksum found in a received data packet. The cut-through checksum is based on data found in a packet header, and thus can be validated before the entire packet is received. This feature allows processing of the received data to begin before the entire packet has been received. Many embodiments will also receive a checksum that is based on the entire packet.

Abstract: A node in a network that receives data from a data source, such as another node. The receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. Thus, a token identifier is preferably neither a physical memory address nor a virtual address.

Abstract: A receiving node sends a token identifier to the data source and receives data from the data source, along with the token identifier. A token identifier identifies a location in memory on the receiving node, but is not the same as an address in the memory. In the described embodiments, a token identifier is an integer value that acts as an index into a token array, which identifies the memory location.

Abstract: Preferred embodiments of the present invention increase the efficiency of access to a constructed list of memory locations, or DMA list by a host processor. In order to circumvent the problem of latency between an I/O device and the host processor, preferred embodiments of the present invention store a copy of the DMA head pointer in the system memory, as well as on the I/O device. When the head pointer data is changed on the I/O device, the I/O device will use DMA to write the updated head pointer back to system memory.

Abstract: A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer, including to the trigger address thereof. For each buffer to which data is written to the trigger address, the buffer output manager automatically outputs the contents of that buffer, responsive to the writing of the data to the trigger address.

Abstract: A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer including to the trigger address thereof. For each buffer to which data is written to the trigger address the buffer output manager automatically outputs the contents of that buffer responsive to the writing of the data to the trigger address.

Abstract: A buffer output manager facilitates automatic self-triggering output of buffer contents. At least one processes writes control data to at least one buffer, the control data being such that a buffer output trigger address can be determined therefrom. For each buffer to which control data is written, a buffer output manager determines the trigger address of that buffer. At least one process writes data to at least one buffer, including to the trigger address thereof. For each buffer to which data is written to the trigger address, the buffer output manager automatically outputs the contents of that buffer, responsive to the writing of the data to the trigger address.

Abstract: The present invention comprises a method and system for peer to peer input output. The present invention is implemented on a computer system having a microprocessor and a packet switched router coupled to the microprocessor. The peer to peer input output system of the present invention defines a data source corresponding to a first device coupled to the computer system. The system then defines a data sink corresponding to a second device coupled to said computer system. The packet switch router is subsequently used to logically implement a data pipe between the data source and the data sink. The system configures the data pipe to provide adequate bandwidth between the data source and the data sink such that a data transfer occurs smoothly and predictably. The data transfer is performed via the data pipe such that the data transfer proceeds independently of any simultaneous second data transfer in the packet switched router.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.

Abstract: A clamping load distributor and top stop disposed and connecting between a fuel injector body and a clamping device. The clamping load distributor functions as an intermediary to transmit the static clamping load from the clamping device to the fuel injector body. The clamping load distributor includes a cylindrically shaped main body having a bore extending therethrough that is disposed adjacent a coupling return spring. A cap is connected to the cylindrically shaped main body and functions as a top stop for limiting the outward axial movement of a mechanical linkage. The restriction on axial movement creates a small gap between the moving mechanical parts to allow a coating of lubrication to be obtained. The main body having a pair of clamp receiving portions formed therein for receiving a clamping load. An annular ring is formed on the bottom side of clamping load distributor radially inward from the clamp receiving portions for contacting the upper deck of the fuel injector body.

Abstract: The present invention comprises a method and system for implementing prioritized communications in a computer system. The present invention is implemented on a computer system having a microprocessor and a plurality of peripheral devices coupled to the computer system. The system of the present invention determines a first priority level and determines a second priority level. The system of the present invention receives a bandwidth allocation request from a software process to transfer data at the first priority level between two or more peripheral devices. The system subsequently allocates a first priority data transfer bandwidth between the devices in response to the request and performs a first data transfer between the devices using the first priority data transfer bandwidth. In addition, the system of the present invention performs a second data transfer between other devices using a second priority data transfer bandwidth. The second data transfer occurs at a second priority level.