Abstract: A bulk semiconductor substrate is provided which has an active area received between at least two undoped silicon dioxide comprising substrate isolation regions. The substrate includes at least two transistor gate constructions received at least partially over the active area. The gate constructions include gates having their sides and tops covered with insulating material comprising at least one of undoped silicon dioxide and silicon nitride. A doped silicon dioxide layer is formed over the active area, the isolation regions and the gate constructions. A patterned masking layer is formed over the doped silicon dioxide layer. The patterned masking layer has a mask opening formed therein which overlaps at least one of the gate constructions and the active area. The substrate is placed within a high density plasma etcher. The etcher has a directly coolable top power electrode, a biasable electrostatic chuck, a focus ring, and directly heatable chamber sidewalls.

Abstract: A bulk semiconductor substrate is provided which has an active area received between at least two undoped silicon dioxide comprising substrate isolation regions. The substrate includes at least two transistor gate constructions received at least partially over the active area. The gate constructions include gates having their sides and tops covered with insulating material comprising at least one of undoped silicon dioxide and silicon nitride. A doped silicon dioxide layer is formed over the active area, the isolation regions and the gate constructions. A patterned masking layer is formed over the doped silicon dioxide layer. The patterned masking layer has a mask opening formed therein which overlaps at least one of the gate constructions and the active area. The substrate is placed within a high density plasma etcher. The etcher has a directly coolable top power electrode, a biasable electrostatic chuck, a focus ring, and directly heatable chamber sidewalls.