Patents by Inventor Dave Pratt
Dave Pratt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978527Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: March 11, 2022Date of Patent: May 7, 2024Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Publication number: 20230058288Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.Type: ApplicationFiled: November 2, 2022Publication date: February 23, 2023Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, Frank Speetjens, Darin S. Miller, Siva Naga Sandeep Chalamalasetty, Dave Pratt, Yi Hu, Yung-Ta Sung, Aaron K. Belsher, Allen R. Gibson
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Publication number: 20230021072Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.Type: ApplicationFiled: September 16, 2022Publication date: January 19, 2023Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, Radhakrishna Kotti, David A. Kewley, Dave Pratt
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Patent number: 11545391Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.Type: GrantFiled: February 11, 2020Date of Patent: January 3, 2023Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, Frank Speetjens, Darin S. Miller, Siva Naga Sandeep Chalamalasetty, Dave Pratt, Yi Hu, Yung-Ta Sung, Aaron K. Belsher, Allen R. Gibson
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Patent number: 11482492Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.Type: GrantFiled: July 10, 2020Date of Patent: October 25, 2022Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, Radhakrishna Kotti, David A. Kewley, Dave Pratt
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Publication number: 20220199123Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: March 11, 2022Publication date: June 23, 2022Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Patent number: 11328749Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: December 18, 2019Date of Patent: May 10, 2022Assignee: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Publication number: 20220013449Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.Type: ApplicationFiled: July 10, 2020Publication date: January 13, 2022Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, Radhakrishna Kotti, David A. Kewley, Dave Pratt
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Publication number: 20210249304Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.Type: ApplicationFiled: February 11, 2020Publication date: August 12, 2021Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, Frank Speetjens, Darin S. Miller, Siva Naga Sandeep Chalamalasetty, Dave Pratt, Yi Hu, Yung-Ta Sung, Aaron K. Belsher, Allen R. Gibson
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Publication number: 20210193189Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: December 18, 2019Publication date: June 24, 2021Applicant: Micron Technology, Inc.Inventors: Raju Ahmed, David A. Kewley, Dave Pratt, Yung-Ta Sung, Frank Speetjens, Gurpreet Lugani
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Patent number: 10685882Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: GrantFiled: May 23, 2017Date of Patent: June 16, 2020Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins
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Patent number: 9828069Abstract: A mooring system (10) for use in mooring a marine device (24) within a fluid (12) subject to flow comprises a mooring line (16) to be secured to an anchor (18) and defining a tether point for a marine device (24), and a loading assembly (20) secured to the mooring line (16) and configured to generate hydrodynamic lift when exposed to flow to apply tension to the mooring line (16). In embodiments of the invention the loading assembly (20) is configured to also generate a buoyancy force, such that tension is applied to the mooring line (16) by a combination of the hydrodynamic lift force and the buoyancy force.Type: GrantFiled: September 17, 2013Date of Patent: November 28, 2017Inventors: Cameron Johnstone, Dave Pratt
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Publication number: 20170256452Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: ApplicationFiled: May 23, 2017Publication date: September 7, 2017Applicant: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins
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Patent number: 9685375Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: GrantFiled: December 5, 2014Date of Patent: June 20, 2017Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins
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Patent number: 9136259Abstract: A method is provided for forming a die stack. The method includes forming a plurality of through-wafer vias and a first plurality of alignment features in a first die. A second plurality of alignment features is formed in a second die, and the first die is stacked on the second die such that the first plurality of alignment features engage the second plurality of alignment features. A method of manufacturing a die stack is also provided that includes forming a plurality of through-wafer vias on a first die, forming a plurality of recesses on a first die, and forming a plurality of protrusions on a second die. A die stack and a system are also provided.Type: GrantFiled: April 11, 2008Date of Patent: September 15, 2015Assignee: Micron Technology, Inc.Inventor: Dave Pratt
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Publication number: 20150087147Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: ApplicationFiled: December 5, 2014Publication date: March 26, 2015Inventors: Dave Pratt, Andy Perkins
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Patent number: 8927410Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: GrantFiled: December 9, 2013Date of Patent: January 6, 2015Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins
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Publication number: 20140099786Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: ApplicationFiled: December 9, 2013Publication date: April 10, 2014Applicant: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins
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Publication number: 20140038479Abstract: A mooring system (10) for use in mooring a marine device (24) within a fluid (12) subject to flow comprises a mooring line (16) to be secured to an anchor (18) and defining a tether point for a marine device (24), and a loading assembly (20) secured to the mooring line (16) and configured to generate hydrodynamic lift when exposed to flow to apply tension to the mooring line (16). In embodiments of the invention the loading assembly (20) is configured to also generate a buoyancy force, such that tension is applied to the mooring line (16) by a combination of the hydrodynamic lift force and the buoyancy force.Type: ApplicationFiled: September 17, 2013Publication date: February 6, 2014Applicant: Nautricity LimitedInventors: Cameron Johnstone, Dave Pratt
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Patent number: 8629060Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.Type: GrantFiled: September 29, 2011Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: Dave Pratt, Andy Perkins